1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY MOSFET Modeling for RF IC Design

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1 1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 MOSFET Modeling for RF IC Design Yuhua Cheng, Senior Member, IEEE, M. Jamal Deen, Fellow, IEEE, and Chih-Hung Chen, Member, IEEE Invited Paper Abstract High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher low-frequency limit is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction. Index Terms High-frequency (HF) MOSFET model, MOSFET modeling, MOS noise, noise modeling, radio-frequency (RF) IC design, radio-frequency (RF) modeling, RFCMOS, RF noise. I. INTRODUCTION WITH fast growth in the radio-frequency (RF) wireless communications market, the demand for high-performance but low-cost RF solutions is rising. This advanced performance of MOSFETs is attractive for HF circuit design in view of a system-on-a-chip realization, where digital, mixed-signal baseband, and RF transceiver blocks would be integrated on a single chip [1] [3]. For RF products, time to market and design cycle reduction depend greatly on the capability of the design environment to predict circuit performance accurately using simulation. To have an efficient design environment, design tools with accurate models for devices and interconnect parasitics are essential. It has been known that for analog and RF applications, the accuracy of circuit simulation is strongly determined by device models. Accurate device models become crucial to predict the circuit performance correctly. MOS transistor models have been originally developed for digital and low-frequency analog circuit design [4] [6] which Manuscript received August 30, 2004; revised December 20, The review of this paper was arranged by Editor A. Wang. Y. Cheng is with Siliconlinx, Inc., Irvine, CA USA ( yuhua.cheng@siliconlinx.com). M. J. Deen and C.-H. Chen are with McMaster University, Hamilton L8S 4K1 ON, Canada ( 2. jamal@mcmaster.ca; chench@mcmaster.ca. Digital Object Identifier /TED focus on the dc drain current, conductances, and intrinsic charge/ capacitance behavior up to the megahertz range. 1 However, as the operating frequency increases to the gigahertz range, the importance of the extrinsic components rivals that of the intrinsic counterparts. Therefore, an RF model with the consideration of the HF behavior of both intrinsic and extrinsic components in MOSFETs is extremely important to achieve accurate and predicts results in the simulation of a designed circuit. Compared with the MOSFET modeling for digital and lowfrequency analog applications, the HF modeling of MOSFETs is more challenging. All of the requirements for a MOSFET model in low-frequency application, such as continuity, accuracy, and scaleability of the dc and capacitance models should be maintained in an RF model. In addition, there are further important requirements of the RF models. 1) The model should accurately predict bias dependence of small-signal parameters at HF operation. 2) The model should correctly describe the nonlinear behavior of the devices in order to permit accurate simulation of intermodulation distortion and high-speed largesignal operation. 3) The model should correctly and accurately predict HF noise which is important for the design of, for example, low-noise amplifiers (LNAs). 4) The model should include the non-quasi-static (NQS) effect so it can describe the device behavior at very high frequency range in which NQS effect will degrade the device performance significantly and cannot be ignored. 5) The gate resistance should be modeled and included in the simulation. 6) The extrinsic source and drain resistances should be modeled as real external resistors, instead of only a correction to the drain current with a virtual component. 7) Substrate coupling in a MOSFET, that is, the contribution of substrate resistance, needs to be modeled physically and accurately using appropriate substrate network for the model to be used in RF applications. 8) A bias dependent overlap capacitance model, which accurately describes the parasitic capacitive contributions between the gate and drain/source, needs to be included. 9) All external components (if it is a subcircuit model) should be physics-based and geometrically scaleable so that the model can be used in predictive and statistical modeling for RF applications. 1 See also for the Mos9 manual /$ IEEE

2 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1287 Fig. 1. MOSFET schematic cross section with the parasitic components [39]. A common modeling approach for RF applications is to build subcircuits based on the intrinsic MOSFET that has been modeled well for analog applications [7] [11]. The accuracy of such a model depends on how to establish subcircuits with the correct understanding of the device physics in HF operation, how to model the HF behavior of intrinsic devices and extrinsic parasitics, and how to extract parameters appropriately for the elements of the subcircuit. Currently, most RF modeling activities focus on the above subcircuit approach based on different compact MOSFET models that are developed for digital and low-frequency analog applications [10] [14]. With added parasitic components at the gate, at the source, at the drain, and at the substrate [9], [15], [16], these models can reasonably well predict the HF ac small-signal characteristics of short channel ( m) devices up to gigahertz range. However, the RF MOSFET modeling is still at a preliminary stage compared with the modeling work for digital and low-frequency analog applications. Efforts from both industry and universities are needed to bring RF MOSFET models to a mature level in further improving the RF models in describing the ac characteristics more accurately, and in improving the prediction of noise characteristics, distortion behavior, and NQS behavior. This paper reviews the efforts of MOSFET modeling for RF applications. Section II analyzes the ac small-signal modeling with emphasis in concepts and basic modeling approaches as well as the data deembedding and model parameter extraction. Section III presents the HF noise modeling with some detailed analysis of channel noise, induced gate noise, and their correlation. Section IV addresses larger signal modeling with the discussion of MOSFET distortion behavior and modeling challenges. II. AC SMALL-SIGNAL MODELING As shown in Fig. 1, a four-terminal MOSFET can be divided into two portions: intrinsic part and extrinsic part. The extrinsic part consists of all the parasitic components, such as the gate resistance, gate/drain overlap capacitance, gate/bulk overlap capacitance, source series resistance, drain series resistance, source/bulk junction diode, drain/bulk junction diode, and substrate resistances,, and. The intrinsic part is the core of the device without including those parasitics. Even though it would be desirable to design and fabricate MOSFETs without those parasitics, they cannot be avoided in reality. Some of them may not be noticeable in dc and low-frequency operation. However, they will influence significantly the device performance at HF. A. Modeling of the Intrinsic MOSFET To meet the requirements discussed above, an RF MOSFET model should be derived with the inclusions of most (if not all) important physical effects in a modern MOSFET, such as normal and reverse short-channel and narrow-width effects, channel length modulation, drain-induced barrier lowering (DIBL), velocity saturation, mobility degradation due to vertical electric field, impact ionization, band-to-band tunneling, polysilicon depletion, velocity overshoot, self-heating, and channel quantization [17]. A compact model includes many mathematical equations for different physical mechanisms. The most important and essential parts are the dc and capacitance models. It has been found that the model accuracy in fittings of HF small-signal parameters and large-signal distortion of an RF MOSFET is basically determined by the dc and capacitance models[18], [19]. In the dc model, the channel charge and mobility need to be modeled carefully to describe the current characteristics accurately and physically, based on which, different physical effects can be added. In modeling the channel charge, physical effects such as short-channel effect, narrow-width effect, nonuniform doping effect, and quantization effect, etc. should be accounted for in order to describe the charge characteristics accurately in todays devices. Mobility will influence the accuracy and distortion behavior of the model significantly [17], [22]. Based on the charge and mobility models, complete equations can be developed with further inclusions of many important physical effects listed above. In order to meet the requirements for both ac small-signal and large-signal applications, the continuity and distortion behavior of the model should be ensured in deriving the equations for these physical effects. In a real circuit operation, the device operates under timevarying terminal voltages. Depending on the magnitude of the time-varying signals, the dynamic operation can be classified as a large- or small-signal operation. Both types of dynamic operation are influenced by the capacitive effects of the device. Many MOSFET intrinsic capacitance models have been developed. Basically, they can be categorized into two groups: 1) Meyer and Meyer-like capacitance models [26] and 2) charge-based capacitance models [4], [27], [28]. The Meyer and Meyer-like models are simpler than charge-based models so they are efficient and faster in computations. Charge-based models ensure the charge conservation and consider the nonreciprocal property of the capacitances in a MOSEFT. These features are required to describe the capacitive effects in a MOSFET, especially for RF applications where the influence of transcapacitances are critical and should be considered in the model. The development of an intrinsic capacitance model of modern MOSFETs is another challenging issue in RF modeling. To meet the needs in RF applications, besides ensuring charge conservation and nonreciprocity, an intrinsic MOSFET capacitance model should at least have the following features such as: 1) guaranteeing model continuity and smoothness in all the bias regions; 2) providing model accuracy for devices with different geometry and different bias conditions; and 3) ensuring model symmetry at the bias of V. B. Modeling of the Extrinsic MOSFET As we discussed above, a MOSFET contains many extrinsic components such as gate resistance, source/drain series resis-

3 1288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 tance, substrate resistance and capacitance, and gate overlap capacitance. It has been well known that the gate resistance impacts impedance matching to achieve maximum power transfer and increases the noise figure of the transistor due to the thermal noise introduced by the gate resistance. Furthermore, the gate resistance also reduces (the frequency at which the maximum available power gain of the device equals to 1), which is an important device parameter in RF circuit design. The gate resistance is in principle a bias-independent component at dc and low frequency, but may contain the contribution of an additional component with bias dependence at HF due to two additional physical effects. One is the distributed transmission line effect on the gate, and the other is the distributed effect or the NQS effect in the channel [7], [15]. The distributed transmission line effect on the gate at HF has been studied [6]. It will become more severe as the gate width becomes wider at higher operation frequency. Therefore, multifinger devices are used in the circuit design with narrow gate width for each finger to reduce the influence of this effect. A simple expression of gate resistance, based on that in dc or low frequency, has been used to calculate the value of gate resistance with the influence of the distributed gate effect (DGE) at HF. However, a factor of is introduced, which is 1/3 or 1/12 depending on the layout structures of the gate connection to account for the distributed RC effects at RF, as given in the following: where is the gate sheet resistance, is the channel width per finger, is the channel length, and is the number of fingers, is the extension of the polysilicon gate over the active region. Complex numerical models for the gate delay have been proposed [29]. However, the simple gate resistance model with the factor for the distributed effect has been found accurate up to 1 /2 for a MOSFET without significant NQS effects [10]. The NQS effect or the distributed RC effect in the channel is another effect that should be accounted for in modeling the HF behavior of a MOSFET. For the devices with NQS effects, additional bias and geometry dependences of the gate resistance are needed to account for the NQS effect [7], [15]. It has been proposed that an additional resistive component in the gate should be added to represent the channel distributed RC effect [7]. As discussed above, when a MOSFET operates at high frequencies, the contribution to the effective gate resistance is not only from the physical gate electrode resistance but also from the distributed channel resistance, which can be seen by the signal applied to the gate, as shown in Fig. 2. Thus, the effective gate resistance consists of two parts where is the distributed gate electrode resistance from the polysilicon gate material and is given by (17), is the NQS distributed channel resistance seen from the gate and is a function of both biases and geometry [7], [15]. (1) (2) Fig. 2. Equivalent gate resistance consists of the contributions from the distributed gate poly resistance and distributed channel resistance [39]. Fig. 3. Equivalent circuit of the substrate network [39]. It has been known that the source/drain resistances are bias dependent. However, a model without the bias dependence can work reasonably well in todays MOSFETs, because the LDD region in these devices with advanced technologies (0.18 m and less) has a very high doping concentration, which results in a weak bias dependence of and. Typically, the source/drain resistances and without including any bias dependence can be described by where and are the parasitic drain and source resistances with unit width, and account for the part of the series resistances without the width dependence. The influence of the substrate resistance is usually ignored in compact models for digital and analog circuit simulation at low frequency. However, at high frequencies, the signal at the drain couples to the source and bulk terminals through the source/drain junction capacitance and the substrate resistance. The substrate resistance influences mainly the output characteristics, and can contribute as much as 20% or more of the total output admittance [8], [10]. It has been known that the substrate components become distributed at HF. Although it is always desirable to have a detailed distributed RC network to account for the contribution of the substrate components, it is too complex to be implemented in a compact model. A good compromise is still to use a lumped RC network, if it is accurate in the required operation frequency range, to simulate the contribution of the substrate components. A simple equivalent circuit for the substrate network shown in Fig. 3 has (3) (4)

4 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1289 Fig. 4. [31]). Illustration of different capacitance components in a MOSFET (after been used to analyze the HF substrate-coupling effect and the characteristics of substrate resistance at HF [30]. Generally, assuming that the device is symmetric between source and drain and that it has no difference between the outer and inner source/drain regions in a multifinger device, we have where is the sheet resistance in the substrate between the source and drain. According to the layout, and should be functions of the channel width of the device. The following equations have been proven by the measurements for the devices with substrate ties, in parallel to the gate, outside the source/drain regions (isolated by shallow trench between the substrate ties and the active region): where and are the substrate resistances per unit-channel width. It has been found that the bias dependence of the substrate resistances is actually very weak for the devices with substrate ties isolated by shallow trench from the active region, and the above simple substrate resistance network is accurate up to 10 GHz [16], [30]. As shown in Fig. 4, the parasitic capacitances in a MOSFET can be divided into the following components: 1) the outer fringing capacitance between the polysilicon gate and the source/drain, ; 2) the inner fringing capacitance between the polysilicon gate and the source/drain, ; 3) the overlap capacitances between the gate and the heavily doped S/D regions (and the bulk region) and ( ), which are relatively insensitive to terminal voltages; 4) the overlap capacitances between the gate and lightly doped S/D region and, which change with biases; 5) the source/drain junction capacitances and ; and 6) the substrate capacitance,. Most of them have been included in models for digital/analog applications [17]. However, additional parasitic capacitance components may have to be added (5) (6) (7) Fig. 5. Illustration of subcircuit model with intrinsic and extrinsic components (after [31]). to the existing models (either intrinsic or extrinsic capacitance models) if they cannot meet the accuracy requirements at RF. The substrate capacitance is an extrinsic capacitance that should be included in a subcircuit model for ultra HF (much higher than 10 GHz) applications. C. Subcircuit RF Model With the consideration of parasitic resistances at the drain, at the gate, at the source, and at the substrate, a complete subcircuit model for a MOSFET at HF can be given in Fig. 5. In the subcircuit model, the characteristics of the intrinsic device is described by a MOS transistor compact model implemented in the circuit simulator, and all the extrinsic components have to be located outside the intrinsic device, so that the MOS transistor symbol in the subcircuit only represents the intrinsic part of the device. 2 For example: 1) the source and drain series resistors have been added outside the MOS intrinsic device to make them visible in ac simulation; 2) the gate resistance is added to the subcircuit model; 3) the substrate resistors are added to account for the signal coupling through the substrate; and 4) two external diodes are added in order to account for the influence of the substrate resistance at HF (the source-to-bulk and drain-to-bulk diodes are part of the compact model but their anodes are connected to the same substrate node, which will short the ac signal at HF so the diodes internal to the compact model should be turned off). Note that the intrinsic substrate node should be connected at some point along the resistor, but simulations have shown that connecting the intrinsic substrate to the source or the drain side has little influence on the simulated ac parameters. In some RF models [8], [10], the intrinsic substrate has been connected to the source side in order to save one node and one component for the subcircuit model. Two external overlap capacitances, and as shown in Fig. 5, with bias dependence can be added, but this is not always required, depending on the compact model used. An equivalent circuit to understand the components (both intrinsic and extrinsic) in the model is given in Fig. 6 [31], where,, and are the differences of the transcapacitances 2 It may include the overlap capacitances at the source, at the drain and at the bulk, depending on the intrinsic compact MOSFET model used in the implementation.

5 1290 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 Fig. 7. Equivalent circuit used for two-step deembedding of measured HF data of MOSFETs (after [31]). Fig. 6. [31]). Equivalent circuit with both intrinsic and extrinsic components (after between the drain and the gate, between the drain and the bulk, and between the gate and the bulk, and given by (8a) (8b) (8c) where and are intrinsic trancapacitances between the source and the drain, and between the bulk and the source and have the following relationships with other capacitances [31]: (9a) (9b) (10a) (10b) (10c) (10d) (10e) where and are intrinsic and extrinsic capacitances between the gate and the source, and are intrinsic and extrinsic capacitances between the gate and the drain, and are intrinsic and extrinsic capacitances between the gate and the bulk, and are intrinsic and junction capacitances between the bulk and the source, and and are intrinsic and junction capacitances between the bulk and the drain [31]. It should be noted that most MOSFET models available in circuit simulators use the quasi-static (QS) approximation. In a QS model, the channel charge is assumed to be a unique function of the instantaneous biases, i.e., the charge responds to a change in voltages with infinite speed. Thus, the finite charging time of the carriers in the inversion layer is ignored. In reality, the carriers in the channel do not respond to the signal immediately, and hence, the channel charge is not a unique function of the instantaneous terminal voltages (quasi static) but a function of the history of the voltages (non-quasi-static [NQS]) [32]. This problem may become pronounced in RF applications, where the input signals may have rise or fall times comparable to, or even smaller than, the channel transit time. NQS effect should be included for an RF model to accurately describe the HF characteristics of devices, if the devices themselves exhibit this effect at the operating frequency. The NQS effect can be modeled with different approaches for RF applications [33]. Ideally, the NQS effect should be included in the core intrinsic model if the model can predict both NQS and noise characteristics without a large penalty in the model implementation and simulation efficiency. NQS modeling is one of the interesting topics in RF modeling. However, it is not a focus here due to the length limitation of this paper. D. Parameter Extraction 1) RF Measurement and Deembedding Techniques: For a model to describe the device characteristics accurately, all important model parameters should be extracted from the measured data. To extract the RF model parameters, on-chip HF measurements are performed by using specifically designed test structures. Also, a deembedding methodology has to be developed to remove the influence of the parasitics in the test structure from the measured raw data in order to obtain the data for the characteristics of the device-under-test (DUT). Different deembedding techniques have been developed based on different calibration test structures [34] [36]. Here, the deembedding procedure based on the above open and short calibration test structures is discussed. Typically, a DUT with parasitics from the test structures can be represented by the equivalent circuit in Fig. 7 [31], where,, and represent the influence of the parallel parasitics and,, and describe the influence of the series parasitics. These parallel elements,, and can be obtained from the measured data of the open structure, i.e., (11a) (11b) (11c)

6 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1291 Fig. 8. (a) Illustration of the necessity of the deembedding of the real part of the measured Y data (after [31]). (b) Illustration of the necessity of the deembedding of the imaginary part of measured Y (after [31]). Fig. 9. (a) Another example to show the importance of the deembedding of the real part of measured Y (after [31]). (b) The figure shows a significant difference between the imaginary part of the measured Y before and after deembedding (after [31]). The series elements,, and can be obtained from the measured data of both open and short structures, i.e., converting from equation: according to the following (12) The measured data corresponding to the transistor can be obtained according to the following equation: (13) Thus, according to the above, the procedures of the two-step deembedding technique can be given as follows. 1) Measure the -parameters (,, and ) for DUT, open and short test structures and convert them to parameters (,, and ); 2) Perform the first step deembedding by removing the parallel parasitics from both and according to the following equations: (14) (15) 3) Perform the second deembedding by removing the series parasitics, converting from, from, (16) Figs. 8 and 9 show the data of the measured and before and after one-step and two-step deembedding [31]. Significant difference between the data before and after one-step deembedding has been observed. Thus, the data deembedding with the open calibration structure is absolutely necessary to extract accurate parameters of an RF model. A minor difference between the data after the one-step and the two-step deembedding indicate that the calibration with the short structure may be ignored for the MOSFETs at the frequency range in this measurement. However, for the device to work at a much higher frequency range, the importance of the calibration with the short structure should be considered. Also, the short calibration may have to be used to obtain the measured data for other devices such as inductors because the devices themselves are very sensitive to the influence of the series parasitics. 2) Parameter Extraction: Depending on the equivalent circuit used in the model, methodologies of HF parameter extraction have been developed [31], [37]. Usually, the -parameter

7 1292 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 analysis of the equivalent circuit is adopted to obtain the necessary equations to extract the values of some resistive and capacitive components. It has been known that the poles due to the terminal resistances (that usually are small because of the large finger numbers) are at a much higher frequency than typical transit frequencies, so that they basically can be neglected when calculating the -parameters and the related quantities. The substrate resistances in the small-signal circuit is also neglected when analyzing the -parameters (,, and except the ) to obtain expressions that are suitable for use in parameter extraction. The parameters related to the dc characteristics are extracted with the data from the dc measurements. The methodologies for the dc model parameter extraction have been well developed [17], [38]. By applying a gate bias high enough to operate the device in strong inversion regime, the intrinsic gate-to-bulk capacitance is small enough and can be neglected. The equivalent circuit for the parameter analysis is obtained [31]. The following approximate equations for -parameters can be obtained: (17a) (17b) (17c) Direct extraction of the ac parameters can be performed from the measured data according to the above equations Im Im Im Re Re Im Re Im (18) (19) (20) (21) (22) (23) Re (24) Im Depending on the measured data, which can be influenced by the design of the test structure, the calibration of the measurement system, the experience of the measurement person, and the accuracy of the deembedding procedures, the values of and extracted from the -parameter measurements may or may not equal the ones extracted from dc measurements. To ensure the dc characteristics predicted by the model parameters extracted from dc measurements not to be disturbed by the possible different and extracted from the measured -parameters, it is recommended that the values of and extracted from dc measurements are used in extracting the ac parameters. In that case, the parameter can be extracted with the following equation: Re Im (25) To extract the parameters for the substrate network, additional analysis for the parameter ( ) is needed. By performing a tedious but straightforward parameter analysis [30], we finally obtain the following equations: Re Re (26a) Im Im (26b) where is the without the influence of, is the output admittance of the substrate network [30], and is the operation frequency. The parameters of and can be obtained as discussed earlier. Thus, the data deembedded from the measured data according to the above equations represents the contribution of the substrate network [39]. To extract the substrate resistance and junction capacitances, we further derive the following equation by doing a -parameter analysis of the substrate network (27) where,, and. These assumptions are valid in the frequency range up to 10 GHz [33]. Therefore, we have Im (28) Re Im (29) The extracted includes the contribution of both the intrinsic capacitance and the drain junction capacitance. The can be separated from the extracted with the measured data at different because is a function of drain bias and is approximately independent of drain bias in the saturation regime. But, typically the capacitance is dominated by. The value of capacitance at zero bias can be extracted from (28) with the measured data at V. The parameters to describe the bias dependence of capacitance can be extracted according to (28) with the measured data at different. Fig. 10 shows the extracted device parameters as a function of frequency with the transistor at the given bias condition. It is shown that those components are frequency-independent in the devices used for this study. In the devices with strong NQS effects, some device components become frequency dependent [40], and a more complex equivalent circuit should be used to understand the device behavior. III. NOISE MODELING Physics-based modeling of the high-frequency (HF) noise sources channel noise, induced gate noise and their correlation in MOSFETs has recently received much intention [41] [49] because the MOSFET-based RF ICs are increasingly used in electronic systems. In this section, different physics-based HF

8 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1293 Fig. 10. (a) Extracted values of R, R, and R at given bias condition (after [31]). (b) Extracted values of C, C, and C at a given bias condition (after [31]). (c) Extracted values of substrate resistance at several different bias conditions [33]. noise models for these noise sources of interest in MOSFETs will be reviewed and discussed. In addition, the methods of implementing these noise sources based on compact MOSFET models for RF applications are presented. A. Modeling of Channel Noise Due to the down scaling of the MOSFET dimension to deep submicron values and the increasing importance of the transistors noise, many publications on the high-frequency channel noise modeling for short-channel MOSFETs have appeared [41] [49]. The channel noise is white (or frequency independent) and can be included in the equivalent circuit (as shown in Fig. 11) by adding a noise current source between the intrinsic drain and source terminals. The conventional channel noise model for long-channel transistors [32] based on the thermal noise theory (or Nyquist theory) and the dc characteristics of MOSFETs successfully predicted the channel noise of short-channel devices operating in the linear region. However, for RF ICs, transistors operate in the saturation region for most applications. It is observed that the channel noise generated in the short-channel transistors operating in the saturation region is higher than the predicted noise by the conventional channel noise models [44], [45], [50]. Therefore, an explanation of the noise enhancement in short-channel MOSFETs becomes crucial for the channel noise modeling of deep-submicron Fig. 11. Noise-equivalent circuit of a MOSFET including parasitic resistance (R, R, and R ), substrate network (D, D, R, R, and R ), enhanced channel noise (i ), and induced gate noise (i ) for RF IC applications. MOSFETs. In this section, the channel noise models [41] [49] will be briefly reviewed. 1) Noise Current Calculation: The total noise current at the drain terminal is obtained by integrating the noise contribution from each section in the channel. There have been two different calculation approaches presented in the literature to compute the total noise spectral density at the drain terminal. The

9 1294 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 first approach is to obtain the noise spectral density contributed from each channel section at the drain terminal, and then integrate along the channel [41] [47]. The second approach is to integrate each noise voltage density along the channel first and then multiply the total spectral density of the noise voltage by, where is the output conductance [48], [49]. The second approach is essentially not appropriate because for a nonlinear resistor like a MOSFET, a local noise fluctuation cannot be directly translated into a terminal fluctuation. Therefore, from the model derivation in [51] and [52], the channel noise current from each section in the channel should be calculated based on the first approach, i.e., (30) where and are the local conductance and the noise voltage fluctuation at the position, respectively. Based on the Nyquist theory and the dc characteristics of MOSFETs in the absence of velocity saturation, (30) can be simplified to [32] (31) where is Boltzmann s constant, is the lattice temperature ( ) at the position, is the local mobility (cm ), is the electron concentration ( cm ) at the position, is the channel width, is the channel length of the transistor, and is the bandwidth. The term is positive because of the negative charge for electrons in n-channel MOSFETs. 2) Modeling of a MOSFETs Channel: After reviewing the calculation method of these proposed models, what is the physical cause of the channel noise enhancement in short-channel devices, and how to properly model the noise enhancement are the two key issues to be solved in the proposed models [41] [47]. In general, these models can be divided into two categories according to the model of the transistor s channel. The first approach is based on a one-section channel model in which the channel (or the inversion charge) only exists in the gradual channel region which is from the intrinsic source terminal to the pinch-off point [41], [42]. The hot-electron effect in this region is proposed as the physical cause of the noise enhancement, and it is included in the noise model by treating the in (31) as the electron temperature. The second approach [43] [47] is to develop the noise model based on a two-section channel model in which the channel of a MOSFET is divided into two regions a gradual channel region of length (region I in Fig. 12) and a velocity saturation region of length (region II in Fig. 12). When a transistor operates in the linear region, is the same as. There are two physical reasons proposed to explain the noise enhancement based on this two-section model extra noise from region II due to the hot-electron effect [43], [44] and the channel length modulation (CLM) effect in region I [45] [47]. The noise models presented in [43] and [44] are questionable because the equations used to calculate the noise contribution from the sections in region II is based on (31) which is only true in the absence of velocity saturation [32], and therefore cannot be applied in region II. On the other hand, because the Ohm s lawis not valid in the velocity saturation region, the local resistance used in the thermal noise equation [32], [52] is not defined. Fig. 12. Cross section of a MOSFET channel divided into a gradual channel region (I) and a velocity saturation region (II). Therefore, the thermal noise theory cannot be applied in region II [53]. 3) Cause of Channel Noise Enhancement: Based on the two-section channel model, there is finite inversion charge in region II, and therefore region II is expected to contribute noise current to the total channel noise. Because of the failure of the thermal noise theory in region II, it was proposed that the diffusion noise becomes the main noise source [53], even though the diffusion current is negligible in this region [54]. The question is how to calculate the noise current based on the diffusion noise theory? According to the approach in [53], the noise current at the drain terminal from a section in region II is calculated by multiplying the noise voltage obtained from the diffusion noise theory by its local conductance. However, based on (30), this approach should predict zero noise current because the carriers in region II travel at their saturation velocities and the carriers will not respond to the local change of the electric field caused by the noise voltage fluctuation (i.e., ). This does not mean that the noise voltage in region II will not contribute noise current at the drain terminal. It might do so by modulating the channel length and create a noise current at the drain terminal. On the other hand, the noise current in region II might be calculated directly from the noise current predicted by the diffusion noise theory, but how to obtain the diffusion constant of the carriers under the high dc electric field directly from measurements becomes the key issue in this approach. Therefore, more investigation is required to characterize the noise contribution from this region. In addition to the extra noise contribution from region II, the channel noise enhancement in short-channel MOSFETs can be explained through the channel-length modulation (CLM) effect [45]. From the derivation of (31) based on the two-section channel model, if we treat the part of the channel in the gradual channel region as a single transistor with the channel length, then the local conductance will become (32)

10 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1295 According to the channel noise derivation in [51] and [52], the mean square value of the noise current delivered to the drain terminal from a local resistance is given by multiplied by the square of its local conductance, and it becomes [45] (33) Because of the local conductance enhancement caused by the CLM effect in short-channel MOSFETs, more noise current power will be delivered to the drain terminal from the same local noise power fluctuation which causes the channel noise enhancement. Finally, the substrate resistance will also contribute some noise current to the drain terminal through the bulk transconductance [55]. 4) Velocity Saturation Effect in Gradual Channel Region: As discussed in [45], the derivation of (33) is based on the assumption that the electric field in the longitudinal direction for most of the sections in the gradual channel region is much less than the critical field, i.e., the velocity saturation effect for sections in region I close to the boundary of regions I and II is ignored. As suggested in [41] and [52], the velocity saturation effect should be included in the channel noise modeling, especially for short-channel devices. If the velocity saturation effect in region I is included by modeling the local mobility with the empirical relation [32], [52] (34) where is the local electric field at the position and is the effective mobility depending on the vertical field only, then the dc drain current becomes B. Induced Gate Noise and Its Correlation With the Channel Noise When transistors operate in the gigahertz range, the random potential fluctuations resulting in the channel noise will be coupled to the gate terminal through the gate oxide capacitance. This noise coupling causes the induced gate noise which is usually correlated with the channel noise [52], [56] [59]. Similar to the channel noise modeling, these proposed models can be characterized into two categories according to the channel model used: the one-section channel model [52], [56] [58] or the twosection channel model [59]. The model proposed in [59] assumes that there is induced gate noise generated in the velocity saturation region (region II). However, as discussed in the previous section, the proposed noise voltage [59] in region II will predict zero channel noise because of the zero local conductance, and therefore zero induced gate noise and zero correlation noise because the induced gate noise is fully correlated with the channel noise [52]. Again this does not mean that there is no induced gate noise generated from region II, but alternative approaches using proper physical mechanisms such as modulation or diffusion noise current should be considered. Another mechanism which might generate the induced gate noise is through the inversion charge variation caused by the substrate noise [55] via the bulk transconductance. In this paper, before the channel noise in region II is fully characterized, the induced gate noise and its correlation with the channel noise are only calculated within region I. Based on the induced gate noise in [52] without the velocity saturation effect and the hot-electron effect, and the channel noise from (33), the induced gate noise power ( ) and its correlation noise power with the channel noise ( ) from a section in region I can be obtained by (35) and (36) where is the local channel resistance at the position. It is difficult to derive an analytical expression for from (35), but it can be observed quantitatively that the local channel resistance is increased due to the velocity saturation effect (i.e., ), where is the local resistance without the velocity saturation effect. This implies that a higher thermal noise voltage is generated from the section at the position close to. However, as can be seen from (32), the local conductance at position including the velocity saturation effect will be decreased because the local mobility is reduced (i.e., ). Therefore, the product is approximately equal to [45]. It has been shown that the maximum difference between these two products is less than 5% [47]. This means that the impact of the velocity saturation effect in region I on the channel noise modeling is not as pronounced as that on the modeling of dc current, and it can be considered as a secondary effect compared to the CLM effect in the channel noise modeling of short-channel MOSFETs. where (37) (38) (39) (40) and is the channel potential at the position referred to the source. Equation (40) is obtained by assuming that the velocity saturation effect for the sections in region I close to the boundary of regions I and II can be ignored and the impact of this assumption was discussed in the previous section. In addition, becomes when transistors operate in saturation. By integrating and over region I, the total spectral densities of the induced gate noise and the correlation noise from the gradual

11 1296 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 channel region are then obtained by the integration of (36) and (37) from to divided by, and they are (41) and where. (42) C. Noise Source Implementation Any physics-based noise model has to be implemented into the circuit simulators before they can be used by IC designers. This is usually done through the software vendor or model developers. Assuming that the noise spectral densities of channel noise and induced gate noise are obtained from either theoretical calculation based on any noise model mentioned in previous sections or experimental results [44], [46], [61], this section provides a simple method to implement the enhanced channel noise and the induced gate noise for RF IC applications by using a subcircuit approach. This approach is general and can work with any compact model (e.g., BSIM, MOS 11 or EKV model) and circuit simulator (e.g., SpectreRF or ELDO). In this paper, BSIM3v3 compact model is used to demonstrate the implementation method based on the noise equivalent circuit shown in Fig. 11. Because most of the circuit simulators cannot handle correlated noise sources, the correlation noise is not implemented in this paper. 1) Enhanced Channel Thermal Noise: The enhanced channel thermal noise shown in Fig. 11 is implemented by using a current controlled current source (CCCS), and its value is determined by the noise current generated by the reference resistance as shown in Fig. 13(a). With the noise flag noimod in BSIM3v3 noise model set to 4, the spectral density of the channel noise generated by the BSIM compact model is given by [63] (43) where is Boltzmann s constant, is the absolute temperature, is the effective mobility, is the effective channel length and is the inversion channel charge. Therefore, the proposed noise power source should only compensate the difference between and. So the value of is determined by [64] (44) Fig. 13. Noise reference circuits to generate noise currents for (a) the enhanced channel noise i and (b) the induced gate noise i shown in Fig ) Induced Gate Noise: The induced gate noise can be naturally generated by using the segmentation method as presented in [46]. However, a disadvantage of this approach is that it increases the number of transistors and therefore the simulation complexity, especially for the distortion analysis. In this paper, the induced gate noise shown in Fig. 11 is implemented by using a current controlled current source (CCCS). Because there is no induced gate noise generated in the BSIM3v3 model and the induced gate noise is proportional to frequency square (as seen in (41)), the task is to find a reference circuit for whose spectral density is proportional to frequency square without worrying about the contribution from the compact model. It is found that the reference circuit shown in Fig. 13(b) can generate the noise spectral density with the desired frequency dependency by a proper selection of the capacitance value and the resistance value as [64] and (45) (46) where is the maximum frequency up to which the simulation will be valid, and represents the coefficient in the versus frequency characteristics, i.e., (47) D. Experimental Results and Discussions After reviewing the noise models from the theoretical view point, the possible candidates based on hot-electron effects [41], [52] and CLM effects [45] [47] will be verified experimentally. The DUTs are fabricated in a 0.18 m CMOS technology with channel width m and channel lengths m, 0.42 m and 0.97 m, respectively. To compare the best fit from different noise models including the hot-electron effect, Fig. 14 shows the extracted (symbols) and simulated (lines) spectral densities of the channel noise versus characteristics for the n-type MOSFETs biased at V. The solid lines are obtained by using the noise model in [45], the inversion charge model in [63] and the channel length model in [60] without including the hot-electron effects. On the other hand, the dotted dashed lines are obtained using the noise model in [52] with the hot-electron effect factor, and

12 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1297 Fig. 14. Extracted (symbols) and simulated (lines) spectral densities of the channel noise S versus V characteristics for the n-type MOSFETs with channel width W=102 6 m and channel lengths L =0:97 m, 0.42 m, and 0.18 m, respectively biased at V = 1:5 V. the dashed lines are obtained based on the noise model in [41] with the fitting parameter. It is shown that the proposed models in [41] and [52] including the hot-electron effect predict slightly different slopes in the versus characteristics compared to the measured data. For the induced gate noise and its correlation with the channel noise, Figs. 15 and 16 show the extracted (symbols) and simulated (lines) spectral densities of the induced gate noise and the correlation noise versus characteristics for the n-type MOSFETs biased at V. The solid lines are obtained by using (41) and (42) and the dashed lines are obtained based on the noise model in [52] with the velocity saturation effect. In addition, the dotted-dashed and the dashed lines are calculated with ( ) and without ( ) the hot-electron effect, respectively. It is shown that the model with the velocity saturation effect, (dashed lines) predicts lower and because of the neglect the enhancement of the local channel resistance as discussed in (35). In addition, the model including the hot-electron effect can reasonably solve the discrepancy in, but it degrades the prediction of. This is because the hot-electron term in [52] enhances the negative value caused by the term in (37) when is close to. This does not mean that the concept of hot-electron effect is proven physically incorrect, but the way of modeling this effect should be reconsidered. On the other hand, as shown in Figs. 15 and 16, the CLM effect does not significantly affect and because the net effect of the appears at the numerator of (41) and (42), not at the denominator as shown in (33) for the channel noise. Therefore, the noise model based on the CLM effect (e.g., models in [45] [47] for channel noise, (41) for the induced gate noise and (42) for the correlation noise) can consistently predict the high-frequency noise performance of a MOSFET. After verifying the physics-based noise sources, they are implemented into circuit simulators, and the next step is to verify the implementation method. Because the induced gate noise is pronounced in the long-channel transistors due to the higher gate capacitance, and it mainly affects the minimum noise figure ( ) and the magnitude of optimized source reflection coefficient ( ) [64], Fig. 17(a) and (b) shows the measured (symbols) and simulated (lines) and versus fre- Fig. 15. Extracted (symbols) and simulated (lines) spectral densities of the induced gate noise S versus V characteristics for the n-type MOSFETs with channel width W=102 6 m and channel lengths L =0:97 m, 0.42 m, and 0.18 m, respectively biased at V = 1:5 V. Fig. 16. Extracted (symbols) and simulated (lines) spectral densities of the correlation noise S versus V characteristics for the n-type MOSFETs with channel width W=102 6 m and channel lengths L =0:97 m, 0.42 m, and 0.18 m, respectively biased at V = 1:5 V. quency characteristics for transistors with two different channel lengths working in the linear region, where the BSIM3 channel noise model is accurate (as seen in Fig. 17(c) for the equivalent noise resistance ). Note that the NQS effect is implemented in the BSIM3 model. All the parameter values are directly calculated based on the BSIM3v3 model parameters without any fitting parameters. From Fig. 17(a) and (b), it is shown that with the proposed induced gate noise model given by (41) and the implementation method, the noise parameters can be accurately predicted. For most of the RF applications, transistors will work in the saturation region. Fig. 18 shows the noise parameters in the saturation region. It can be seen from Fig. 18(a) and (b) that the induced gate noise also has a significant impact in the modeling of and of long channel transistors working in the saturation region. On the other hand, as shown in Fig. 18(c), the enhanced channel noise due to the CLM effect can be accurately included in the simulation through the help of. For short-channel devices, Fig. 19 shows the versus frequency characteristics for a 0.18 m transistor working in the saturation region. All short-channel effects are taken care of by the BSIM3 model. The induced gate noise does not affect the as much as it does in long-channel transistors.

13 1298 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 Fig. 17. (a) Measured (symbols) and simulated (lines) NF versus frequency characteristics for long-channel transistors working in the linear region. (b) Measured (symbols) and simulated (lines) j0 j versus frequency characteristics for long-channel transistors working in the linear region. (c) Measured (symbols) and simulated (lines) r versus frequency characteristics for long-channel transistors working in the linear region. On the other hand, the CLM effect becomes the most important effect in the noise modeling of short-channel transistors. Note that if the channel width of the transistor is not wide enough, both measured and simulated will fluctuate as shown in Fig. 19, and then it becomes difficult to measure the noise parameters of short-channel devices accurately. IV. DISTORTION AND LARGE SIGNAL MODELING The capability of a HF device model to predict large-signal and intermodulation distortion is very critical. A good RF model should predict well not only the ac small-signal and noise characteristics, but also large-signal distortion. It has been studied that MOSFETs exhibit fairly constant distortion characteristics over frequencies, implying a relatively high low-frequency limit (LFL), as show in Fig. 20 [18], [19]. The LFL can be considered as a frequency below which the distortion characteristics behave like those in low frequency. This is a very useful characteristic of CMOS technology for RF design, as its HF distortion behavior is mainly determined by the dc and low-frequency ac characteristics of the device. Therefore, the MOSFET distortion behavior should be well predicted by a model generated with an appropriate dc and ac modeling procedure. The LFL decreases as the gate length of the MOSFET increases. The LFL behavior of MOSFETs is advantageous for the design of active RF applications. For most of the active blocks, such as LNAs, drivers, and active mixers, where a certain amount of amplification is always desired, the transistors are selected under the condition that the operating frequency is mostly below the LFL of the transistor. Another important behavior observed from measured data is the distortion behavior of MOSFETs in different operation regimes. As shown in Fig. 21, as the transistor operates in the linear region, the distortion behavior changes dramatically with. However, as the device enters into saturation, it exhibits a fairly constant distortion behavior over, even for the device with a short. This characteristic simplifies the design for large-signal application, such as power amplifierss and drivers, where a constant distortion behavior can be assumed for a transistor with very large-signal swing at the output, as long as the transistor maintains its operation in the saturation regime. It has been reported that a model with good fittings in both dc (both current and the derivatives) and ac (both capacitance and -parameters) characteristics can predict the distortion behavior of a transistor up to a operating frequency at which the device is still capable of delivering decent power gain, if physical and proper parameter extraction procedures are adopted [18], [19]. Fig. 22 shows the comparison results between measured data and the subcircuit RF model [18], [19]. The model can accurately describe the fundamental, second and third harmonics

14 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1299 Fig. 18. (a) Measured (symbols) and simulated (lines) NF versus frequency characteristics for long-channel transistors working in the saturation region. (b) Measured (symbols) and simulated (lines) j0 j versus frequency characteristics for long-channel transistors working in the saturation region. (c) Measured (symbols) and simulated (lines) r versus frequency characteristics for long-channel transistors working in the linear region. Fig. 19. Measured (symbols) and simulated (lines) NF versus frequency characteristics for a short-channel transistor working in the saturation region. over a wide range of bias conditions and frequencies. The model is generated with special care about parameter extraction based on dc and ac but no additional extraction effort against the data of distortion characterization [39]. The influence of some important device parameters such as oxide thickness and channel length to the distortion behavior Fig. 20. Measured P versus drain current I for a m m device (finger = 10, channel width per finger = 12 m, and channel length = 0:36 m) at four different frequencies (f = 50MHz, 100 MHz, 900 MHz, and 1.8 GHz, respectively) [19]. has been studied [18], [19]. It has been known that the distortion behavior as a function of does not strongly depend on

15 1300 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 Fig. 21. Measured P versus drain current I for the device at several different drain biases when f =1:8 GHz and P = 015 dbm; (a) drain-source voltage V =0:5 V, (b) V =1V, (c) V =1:5 V, and (d) V =2:5 V [19]. Fig. 22. Modeled (solid lines) and measured (symbols) P s versus the drain current I for the m m device at different frequencies when V =0:5Vand P = 010 dbm; (a) f =50MHz, (b) f = 100 MHz, (c) f = 900 MHz, and (d) f =1:8GHz [19]. the effective gate length, even if the versus characteristics is significant changed. Similar steadiness can also be observed in the simulation with variation [18], [19]. This weak dependence of the distortion behavior on and is extremely useful for design of a MOSFET stage at high frequencies, because the distortion behavior can be readily estimated with a model fitting well the dc characteristics. A superior distortion performance can be achieved by taking advantage of the third harmonic dip, i.e., the sweet spot, without considering the potential variation over and. It has also been found that the distortion behavior of a MOSFET strongly depends on the saturation velocity ( ) and the effective mobility ( ) [18], [19]. The change in saturation velocity significantly influences the distortion behavior even if is represented as a function of. Also the third harmonic dip, i.e., the sweet spot, moves along with the versus curve shift, which can be observed as indicated in the figure. Compared to the distortion simulation with variation, where a greater than change in is introduced, but only a little change is observed in the distortion simulation, the distortion sensitivity on is manifested even at low frequencies, i.e., 50 MHz. This is because the dc of a MOSFET depends nonlinearly on and its effect permeates to all the frequencies. The saturation velocity has effect only when the device operates in the saturation region, i.e., when the channel is pinched off near the drain region at high s, but the effective mobility has similar dominant effect on at all operating regimes. The effect of the mobility to the distortion simulation at low s, where is changed so that the drain current is altered. Similar to that of, the effect of also moves the third harmonic dips along with the versus shift as indicated in the figure. Although only low simulation is shown here, the same level of influence of exhibits at also high, as it determines at all operating regimes. As one of the most important short-channel effects, the draininduced barrier lowering (DIBL) alters the channel current drive through changing the effective threshold voltage. The sensitivity

16 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1301 of the distortion to DIBL increases as the drain voltage increases [18], [19]. The DIBL effect on the distortion is most significant when the device operates at moderate region, i.e., when is slightly higher than the. The DIBL effect to distortion decreases as increases. Moreover, when a MOSFET is completely off, i.e., at, a MOSFET should behave very linearly as compared with that at any active operation. Therefore, the effect of DIBL to distortion appears only at a small window for the technology we present here. As the channel length decreases, the sensitive window as a percentage of the total range allowed for reliability should be broadened. It should be noted that the above discussion is primarily on the HF distortion behavior of a MOSFET when used in an active operation, as in an amplifier. For MOSFETs employed in hard-switching application, i.e., hard turn on and turn-off, such as in a passive mixer, the distortion behavior is different and specific treatment is needed to use BSIM3v3 model for accurately predicting the distortion behavior. The distortion behavior of a MOSFET used as a switch is very important in RF circuit design and further efforts are needed to develop MOSFETs models for such applications. Also, as a broad-band 1-tone measurement provides the most insightful and direct representation on the correlation of the device nonlinearity to the harmonic outputs, for which modeling methodology is proposed in predicting the large-signal distortion behavior of a MOSFET, the intermode modulation products of a MOSFET are often of interest from a designers point of view. Efforts for another level of verification are needed, based on which, further modeling work may be required. V. SUMMARY MOSFET modeling for RF applications has been discussed. The modeling of both intrinsic and parasitic components in MOSFETs is crucial to describe the HF behavior of MOS devices operated at GHz frequencies. The analysis of equivalent circuits with intrinsic and extrinsic components indicates the importance of the some resistive components (such as gate, source, drain and substrate resistance) and some capacitive components (such as,,,, as well as the transcapacitance, and ). An RF model with accounting for the contributions of both the polysilicon gate resistance and distributed channel resistance may be adequate to predict accurately the HF characteristics of MOSFETs. Also, a physical and accurate model for the substrate components is critical in an RF model. Furthermore, procedures of HF model parameter extraction are discussed with detailed description of the HF measurements and data deembedding. An RF model including NQS effect is desirable without introducing penalty in complex implementation and simulation time. Noise modeling is also discussed by analyzing the theoretical and experimental results in thermal noise modeling. For the channel noise models, the CLM effect is the major cause for the enhanced channel noise in short-channel MOSFETs. It begins to have an impact on the devices with channel lengths shorter than 0.5 m. On the other hand, the impact of the velocity saturation effect and the hot-electron effect in the gradual channel region seem to be negligible in the channel noise modeling of deep submicron MOSFETs. The channel noise is frequency independent and will increase when the channel length is reduced. This can be caused by the CLM effect and the noise contribution for substrate resistance through. On the other hand, and are proportional to and, respectively, and they both decrease when the channel length is reduced because of the decrease of. From the simulated noise parameters with the noise sources implemented, it is found that the induced gate noise has strong impact on the noise performance of long-channel devices, especially for and. On the other hand, for short-channel devices, the enhanced channel noise will play the dominant role in the prediction of their noise performance. Further efforts are needed to model the induced gate noise, the correlation with channel thermal noise and its influence to the circuits at RF. The distortion behavior of MOSFET is reviewed. The fact that MOSFETs have much higher LFLs as compared with BJTs is useful for both RF IC design and modeling. An RF model with accurate dc and ac fitting can predict the distortion behavior of a device up to a very high frequency, enabling prediction of distortion behavior with the given modeling methodology. A study of the sensitivity of device distortion behavior to physical effects is discussed. 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18 CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1303 Yuhua Cheng (M 96 SM 99) received the B.S. degree from Shandong University, Jinan, China, the M. S. degree from Tianjin University, Tianjin, China, and the Ph.D. degree from Tsinghua University, Beijing, China, in 1982, 1985, and 1989, respectively, all in electrical engineering. In 1990, he joined in the Institute of Microelectronics (IME), Peking University, Beijing, as a Research Fellow. From 1992 to 1996, he was an Associate Professor in the IME and the Department of Computer Science and Technology, Peking University. From 1994 to 1995, he was a Visiting Professor at the University of Trondheim, Norway, and a Research Fellow of the Norwegian Research Council. From 1995 to 1997, he was a Research Associate at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, where he was working on the BSIM3 model development and providing technical support to the BSIM3 users from both industry and academics. He was the Project Coordinator of the BSIM3v3 model development and was one of the principal contributors of the BSIM3v3 model that has been chosen as an industry standard model for IC simulation by the Electronics Industry Association/Compact Model Council. In 1997, he worked in Cadence Design Systems as a Member of the Consultant Staff. From 1997 to 2004, he worked for Skyworks Solutions (formerly Conexant Systems), where he was a Senior Manager of the device (bipolar, MOS and passive) modeling and technology service team responsible for mixed-signal/rf device modeling and CMOS/BICMOS technology evaluation/support for various (ASIC, mixed-signal, RF) circuit designs. He is currently the President and CTO of Siliconlinx, Inc., which offers products and services to bridge the gap between IC designers and manufacturing foundries. His interests include CMOS/BICMOS technologies, high-speed bulk and silicon-on-insulator (SOI) devices, BJT/MOS/passive device modeling, physical verification and parasitics extraction, and mixed-signal/rf IC design. He has authored and coauthored over 80 research papers, several book chapters, and the books MOSFET Modeling & BSIM3 User s Guide (Norwell, MA: Kluwer, 1999) and Device Modeling for Analog/RF Circuit Design (New York: Wiley, 2003). Dr. Cheng has served on technical program committees in several international conferences including the IEEE Custom Integrated Circuits Conference (CICC) and IEEE Radio Frequency Integrated Circuits Symposium. He serves in the regions/chapter committees of IEEE Electron Devices Society (EDS) and is the Vice-Chair of the North America West subcommittee for regions/chapters (SRC-NAW) of the EDS regions/chapters Committee. He is an EDS Distinguished Lecturer. M. Jamal Deen (F 03) was born in Georgetown, Guyana. He received the B.Sc. degree in physics and mathematics from the University of Guyana, Georgetown, and the M.S. and Ph.D. degrees in electrical engineering and applied physics from Case Western Reserve University (CWRU), Cleveland, OH, in 1978, 1982, and 1985, respectively. From 1978 to 1980, he was an Instructor of physics at the University of Guyana, and from 1980 to 1983, he was a Research Assistant at Case Western Reserve University. He was a Research Engineer from 1983 to 1985 and then an Assistant Professor from 1985 to 1986 at Lehigh University, Bethlehem, PA. In 1986, he joined the School of Engineering Science, Simon Fraser University, Vancouver, BC, Canada, as an Assistant Professor, and from 1993 to 2002, he was a Full Professor. In 1999, he assumed his current position as Professor of electrical and computer engineering, McMaster University, Hamilton, ON, Canada. In July 2001, he was awarded a Senior Canada Research Chair in Information Technology. He was a Visiting Scientist at the Herzberg Institute of Astrophysics, National Research Council, Ottawa, ON, in summer 1986, and spent his sabbatical leave as a Visiting Scientist at Northern Telecom, Ottawa, from 1992 to He was a Visiting Professor in the Faculty of Electrical Engineering, Delft University of Technology, Delft, The Netherlands, in the summer of 1997 and a CNRS Directeur de Recherche at the Physics of Semiconductor Devices Laboratory, Grenoble, France, in the summer of 1998, and at the Université de Montpellier, France from 2002 to He has edited two research monographs and eight conference proceedings. He has written 14 invited book chapters, has been awarded six patents, has published more that 300 peer-reviewed articles, and has given more than 60 invited/keynote/plenary conference presentations. His current research interests include physics, modeling, reliability, and parameter extraction of semiconductor devices, optical detectors and receivers, polymer and organic semiconductor devices, and low-power, low-noise, high-frequency circuits. He is Executive Editor of Fluctuations and Noise Letters and a member of the editorial board of Interface, an Electrochemical Society journal. Dr. Deen was awarded the 2002 Thomas D. Callinan Award from the Electrochemical Society Dielectric Science and Technology Division, and the Distinguished Researcher Award, Province of Ontario in July, He is a Distinguished Lecturer of the IEEE Electron Devices Society. He is currently an Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES. He was elected a Fellow of Engineering Institute of Canada and a Fellow of The Electrochemical Society. He is a member of Eta Kappa Nu and the American Physical Society. He was a Fulbright-Laspau Scholar from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, and an NSERC Senior Industrial Fellow in Chih-Hung Chen (S 95 M 03) received the B.S. degree in electrical engineering from the National Central University, Chungli, Taiwan, R.O.C., the M.S. degree in engineering science from Simon Fraser University, Burnaby, BC, Canada, and the Ph.D. degree in electrical and computer engineering, McMaster University, Hamilton, ON, Canada, in 1991, 1997, and 2002, respectively. For three consecutive summers from 1998, he was with Conexant Systems Inc., Newport Beach, CA, where he was involved in the high-frequency noise characterization and modeling of MOSFETs and BJTs. During the summer of 2001, he was with Transilica Inc. (now Microtune Inc.), San Diego, CA, where he was engaged in the design of differential LNAs and VCOs for Bluetooth. In 2002, he joined the Faculty of McMaster University, as an Assistant Professor of electrical and computer engineering, where his research interests are high-frequency noise characterization and modeling of MOSFETs and design of low-noise, RF CMOS integrated circuits for wireless applications. Dr. Chen was awarded the 2002 Dean s Award of Excellence in Graduate Research at McMaster University and was the Co-Recipient of the Best Invited Paper Award from the 2002 IEEE Custom Integrated Circuits Conference (CICC).