cost and reliability; power considerations were of secondary importance. In recent years. however, this has begun to change and increasingly power is

Transcription

1 CHAPTER-1 INTRODUCTION AND SCOPE OF WORK 1.0 MOTIVATION In the past, the major concern of the VLSI designer was area, performance, cost and reliability; power considerations were of secondary importance. In recent years. however, this has begun to change and increasingly power is being given more weightage compared to area and speed. Low power. yet high throughput and computationally intensive circuits are becoming a critical application domain. One driving factor being the trend in the growing class of personal computing devices (digital pens, audio and video based multimedia products). portable systems like pacemakers, as well as wireless communication and imaging systems which demand high speed computation, complex functionality and often real-time processing capabilities with low power consumption. Another critical driving factor is that excessive power consumption is becoming the limiting factor in integrating more transistors in a single chip or on a multi-chip module. Unless power consumption is drastically reduced. the resulting heat will limit the feasible packing and performance of VLSI circuits and systems. Circuit synthesized for low power are also less susceptible to run-time failures.

2 Modern Application Specific Integrated Circuits (ASIC's) 'are increasingly becoming mixed signal types to realize system on chip (SOC) where digital and analog, circuits are integrated on the same chip. Low power reduction in digital is related to issues characteristic of digital design approach [I]. The present thesis is concerned with low power analog design where the related issues are Issues Voltage Scaling Implications Compliance to maintain MOSFET in saturation Dimensional Scaling Subthreshold and Moderate Short channel effects Small range of operation region of operation. Current mode operation New architectures Modeling standards and benchmarks Continuity in conductances and capaitances. Charge based, threshold based, potential based models.

3 Moderate and weak inversions are increasingly important and unavoidable regions for device operation in integrated circuits using advanced CMOS technologies. Scaling trends in deep submicron technologies limit the available range of voltage in strong inversion due to supply-voltage reduction and threshold voltage non-scalability. On the other hand, operation in moderate inversion is attractive in terms of increased transconductance efficiency and voltage gain. In most of the work reported in literature [2,3,4,5,6], analog circuits have been designed using traditional, empirical MOSFET models wherein different sets of equations are used for devices operating in strong and weak inversion with discontinuity in moderate inversion, thus incurring severe errors in these important operating regions. With the scaling of device feature size and supply voltage, the level of inversion of MOS devices, also known as inversion coefficient (IC) and defined as the ratio of the drain saturation current to the intrinsic current which is proportional to the W/L ratio of MOS transistor, vary in a given circuit requiring single piece device model valid for all inversion levels. In recent years, some attempts of MOS modeling have been made to have oneequation model for all the operating regions. [7][8][9][10]. EKV [11] based model uses extrapolation, surface potential based models such as MM1 1 [9] requires heavy computational overhead and SPICE[8] has evolved to become empirically driven, complex and regional leading to continuity problems in transition regions requiring non-physical smoothing function. L. 3

4 1.1 The ADVANCED COMPACT MOSFET (ACM) MODEL MOSFET models included in circuit simulators can be classified into the following three categories: Analytical model Stable lookup models Empirical models Most of the models in current use are analytical. MOSFET analytical models are based on either the regional approach or surface potential formulations, or semi-empirical equations. Models based on the regional approach use different set of equations to describe the device behavior in different regions. In the regional approach, the weak and strong inversion regions are generally bridged by using a non-physical curve fitting[l 1]. Models based on surface potential formulation are inherently continuous; however, they demand the solution of an implicit equation for the surface potential. Semi-empirical models take the risk of becoming neither scalable nor suited for statistical analysis. The ACM Model is a charge-based physical model. All the large-signal characteristics (currents and charges) and the small-signal parameters ((trans)conductances and (trans)capacitances are given by single-piece expressions with infinite order of continuity for all regions of operation. The ACM model preserves the structural source-drain symmetry of the transistor and uses a reduced number of physical parameters. It is also charge-conserving and has explicit equations for the MOSFET (trans)capacitances. 4

5 The features of the ACM model can be summarized as follows: single-piece expressions with infinite order of continuity for all regions of operation source-drain symmetry of the transistor charge-conserving equations physically based. equations for the dependence of carrier mobility on tranversal field, carrier velocity saturation, and saturation voltage dependence of electrical parameters on geometry independence of technology easily measurable parameters Some advantages of the ACM Model over BSIM are the use of simpler expressions to describe all regions of operation, the symmetry of the MOSFET is maintained, and requirement of a smaller number of device parameters. Moreover, all the ACM parameters have a strong physical basis. The Advanced Compact MOSFET (ACM) model is thus a current based model proposed in [10],with one-equation for all regions including weak, moderate and strong inversion. The first-order ACM model has been successfully applied in low power analog design [7][10][12][13]. In addition to its computerimplemented version [14] where most of the equations are charge based, it is also extremely useful for analog design by hand calculations.

6 1.1.1 The ACM First Order Model ACM is a physics based MOSFET Model described by a small set (approx. 11) of parameters [15]. The use of the substrate voltage as the reference voltage allows for a symmetric role of source and drain. Hence ACM is appropriate to simulate low-voltage circuits and those sensitive to charge variations. In most analog applications, MOSFETs are biased in the saturation region of operation to achieve high transconductance and low output conductance. The first order ACM model predicts a drain current (' D) in saturation and at all levels of inversion that is given by the equation [10] V PO V I D In + e t (1 + os ) where V = V G V TO (1.2) PO is the pinchaf voltage in equilibrium; V G,V s are the gate and source voltages respectively with respect to bulk (substrate); V[)s is the voltage between drain and source; V 1.0 is the threshold voltage in equilibrium, 2 is the channel length modulation parameter; W and L are the width and length of the MOS transistor, cl), is the thermal voltage, n is the subthreshold slope factor slightly dependent on V G, greater than one and usually less than two (derivative of gate voltage with respect to pinch-off voltage). 6

7 The intrinsic current I and the inversion coefficient (IC) are defined by the equations, 2 1.,u nc (), 2 (1.3) IC = Id W L = Id (1.4) where C is the gate oxide capacitance/ unit area, t' is the low field mobility and I is the normalized current also known as the specific current. The Inversion Coefficient (IC) indicates the inversion level of the transistor. weak inversion I< /C moderate inversion and ic>loo - strong inversion The expression for terminal voltages of the MOSFET in saturation in terms of the inversion coefficient is derived in [10] as ( )[-11+ IC 2 + In(V1 + /C IA for nmos(pmos) (1.5) VDsat VP = ( )[1n(V1 + IC -I)-5] for nmos(pmos) (1.6) The three small signal parameters : gate transconductance (g ngb), drain conductance (g db) and source transconductance (2 ) can be obtained by the differentiation of eq(1.1) as follows. I D :54 = (I nigh 6V D /70 VI /C I gb (1.7) g --- (1 ) = nll) c5v D D S' (1.8) db 7

8 - nub sb 1 ( 1 = D ) D 01 + K ' + I (1.9) The ACM Second Order Model Although the first order model provides an analytic point of view for circuit design, it yields poor representation of MOSFETs with even moderate widths and lengths, since important second order effects are neglected. A more complete and complicated ACM model considering second order effects is described in [14] using charge based equations. This model provides a representation of following second order effects. Vp dependence on V o V s due to drain induced barrier lowering. Surface mobility reduction by gate induced vertical field Surface mobility reduction due to carrier velocity saturation Dependence of /1 upon operating point. In the saturation region, the drain current I DS considering second order effects is given as DS w -os / In I +e P L AL + L dd L -t v (1.10) where intrinsic current / 0 pinch-off voltage V 1, and channel shortening factor AL + L - dd, which model small geometry effects, are functions of bias. It AL + L should be noted that if / os is replaced by 1 0 and (1 dd )- is replaced L by ( / D ) then eq(1.10) will reduce to the first order current eq(1.1). The term models the second order effects of surface-mobility modulation and velocity saturation.

9 (a) Channel Length Modulation As modeled in [14),the channel shortening factor AL + L dd is given as L AL + Ldd 2(LD) + L dd where L L V V L dd = ALc ln[l + DS DsAT L c. UCR1T UCRIT- v MAA. /4) L c AL, is the shrink in channel length, X. is the Junction depth, LD is the Lateral diffusion, is the permitivity of S, UCRIT is the longitudinal critical field for mobility degradation, V MAX is the saturation velocity (m/sec), pt o is the low field mobility (cm 2/V.$) Also L e, = L AL L dd where.1_, 11 is the effective channel length. (1.15) (b) Drain Induced Barrier Lowering (D1BL) Considering DIBL effect the pinchoff voltage is obtained as V1. = V 1. '0 + n + V (1.16) where VP0 2 VG V" ) (V PHI \2 PHI (1.17) n =1 + 2V PHI +111 (1.18) V. 1.0 is the threshold voltage in equilibrium,y(gamma) is the body effect lactor, a (SIGMA) is the DIBL coefficient, PHI is a fitting parameter nearly equal to 20, OF is the Fermi potential. The term a (SIGMA) models the 9

10 dependence of pinchoff voltage on V D and is set to zero the drain induced barrier loweririg effect is eliminated, then eq(i.15) reduces to the pinch off voltage of the first order model as is given by eq(1.2) (c) Mobility degradation effect Mobility depends upon the vertical surface electric field, and decreases for large values of pinchoff or gate bias voltages. This is modeled by the equation IA 0 I-1 = \IV + PHI O(THETA) is mobility reduction coefficient due to transversal field. (1.19) (d) Effect of Velocity saturation Velocity saturation of channel carriers lowers the device conductance and is modeled in ACM as = 43 dos VMAX dx UCRIT dx =- P In L eg UCRIT V P -VS 1+e 119 ' (1.20) where Os is the surface potential The drain current expression for MOSFET in saturation considering second order effects can be rewritten as V P Vs -1 11n 1+e (Pt 1 I) 11 0 W en' CI) - nc ox \ 1+0y.\/Vp +PHI, L eq 2 I + (P, L «^ UCRIT In VP Vs (19, 1+e (1.21) The present thesis uses ACM model and explores its utility in the design of low power analog design using a few representative designs as the vehicle of experimentation. 10

11 1.2 SCOPE OF WORK The work presented in the thesis evolves around the following topics: Development of ACM small signal parameter model considering second order effects valid for all levels of inversion (strong, moderate and weak). 2. Design and performance of single transistor amplifier configuration for different inversion levels and determination of optimum transistor inversion level for maximum gain for a given unity gain frequency fr. 3. Development of design guidelines for a 2-stage CMOS operational amplifier to meet given specifications without any design iterations and valid for all levels of inversion. 4. Study of mismatch errors for the standard current mirror configurations at all inversion levels. 5. Development of scaling rule for MOSFET with reduction in power consumption and its application to an amplifier design. 1.3 ORGANIZATION OF THE THESIS The work presented in the thesis is organized in 7 chapters contents of which are briefly given below. Chapter 1 introduces the rationale of investigating low-power CMOS analog design at different inversion levels. Motivation and need of development study of the analog blocks viz. MOS amplifier, operational amplifier and current mirror are justified. Chapter-2 describes the development of the small signal MOSFET model considering second order effects. The second order effects such as CLM, DIBL. and velocity saturation are represented as different components of the drain, gate and source transconductances and are compared at different inversion levels. Sensitivity studies have been carried out for these parameters.

12 In Chapter-3, the single stage amplifier design is optimized for maximum gain Bandwidth. The common source amplifier is found to give maximum gain at a given unity gain frequency J. when operated at an optimum -inversion level of 90. Chapter 4 gives the details of 2-stage CMOS operational amplifier design. Analytical expressions using the ACM (Advanced Compact MOSFET) model valid for all inversion levels are derived for all the parameters of the operational amplifier and design guidelines were developed for meeting given specifications of operational amplifier. In Chapter 5 development of practically useful formula, for estimating the nominal value of direct current transfer ratio a and the tolerance limits on it, arising from mismatches in operating conditions and dc parameters of the MOS transistors used in standard current mirrors, at different inversion levels, is presented The optimum scaling for reduction in power consumption is described in Chapter 6. The scaling laws are applied to single stage amplifier. using the ACM model. Finally, conclusions and future scope of work is summarized in Chapter-7 12