Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
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1 Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM Jun-Fu Huang, Victor C.Y. Chang, Sally Liu, Kelvin Y.Y. Doong*, and Keh-Jeng Chang** SPICE Core Department, TSMC, Hsinchu Science-Based Industrial Park, Taiwan * PF2, R&D Division, TSMC, Hsinchu Science-Based Industrial Park, Taiwan ** Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan
2 Acknowledgements The authors want to express their gratitude to the logistic supports of TSMC management during this research experiment. They also want to acknowledge the helps of Dr. Li-Fu Chang of Clear Shape Technologies. Jan. 23, 2007, P. 2
3 Outline Random vs. systematic BEOL variations BEOL profile based random variations Monte Carlo (MCGRC) simulations 2-dimensional capacitances 3-dimensional capacitances Validating corners for SSTA Conclusion Jan. 23, 2007, P. 3
4 Random vs. Systematic BEOL Variations BEOL profiles are the geometrical dimensions and material properties of the back-end of the line, i.e. the interconnects. Systematic variations, deterministic in nature, with a varying trend and pattern of BEOL profiles Methods to correctly include OPC, dummy fill, etc. Random variations, a stochastic phenomenon without a clear trend or pattern of BEOL profiles Statistical modeling and timing closure for chip designs. Ref. [1] [2] Jan. 23, 2007, P. 4
5 Targeting BEOL Random Variations Replicating structures with identical environments; Avoiding systematic variations; Avoiding spatial variations; Avoiding measurement noises; Concentrating on on-chip variations. Jan. 23, 2007, P. 5
6 Profiling the Cu-Based Node Top Metals M5 M5 M5 M4 M4 M4 M4 M3 M3 M3 M3 M2 M2 M2 M2 M1 M1 M1 M1 PO PO PO STI PO Substrate Source: Unpublished TSMC 2001 document Jan. 23, 2007, P. 6
7 Monte Carlo (MCGRC) Simulations Random parameters of BEOL profiles that affect capacitance and resistance: (-3σ~ +3σ) Top and bottom plates/grids thickness plus pitch when 3D Metal signal lines thickness and pitch Thickness / ε r of IMD between top and bottom plates Top plate IMD M M M IMD Bottom plate Jan. 23, 2007, P. 7
8 Three Main Experimental Structures Dense 2-D RC structures Signal lines between two adjacent plates Sparse 2-D RC structures Signal lines between two far-away plates 3-D structures ASIC-style real 3-D lines in 3-D environments Jan. 23, 2007, P. 8
9 2-Dimensional Capacitances Source: Unpublished TSMC 2001 document Jan. 23, 2007, P. 9
10 RSS of BEOL Profiles for MCGRC Skew all IMD between the top plate and the lines based on RSS Skew all IMD between the lines and the bottom plate based on RSS. Top plate Skew by root-sum-square M M M Skew by root-sum-square Bottom plate Jan. 23, 2007, P. 10
11 A 3-Dimensional Structure Jan. 23, 2007, P. 11 Ref: [4]
12 The Cross Section of the 3-D Structure Note: M i-1, M i, M i+1, M i+2, and the surrounding IMD layers are all 3-D and their profiles are varying. Jan. 23, 2007, P. 12
13 Jan. 23, 2007, P D Random Capacitance Variations
14 Recently Published BEOL Variations Ref. [3] Jan. 23, 2007, P. 14
15 Measured BEOL Variation Patterns R_normalized Sub-100nm BEOL Silicon data C_normalized Model corners Jan. 23, 2007, P. 15
16 MCGRC BEOL Variation Patterns M4-M3-M2 2.10E E-01 C_best R_Normalized 1.90E E E-01 RC_best Typical RC_worst MC_simulation corner_model 1.60E-01 C_worst 1.50E E E E E E E-01 C_Normalized Note: The above should replace Figure 10 of Page 224, ASPDAC07. Jan. 23, 2007, P. 16
17 Revising Our Corner Models M5-M3-M1 9.00E-02 R_Normalized 8.80E E E E E E-02 MC_simu cur_corner_model new_corner_model 7.60E E E E E E-01 C_Normalized The above revision happens for sparse and wide metals. Jan. 23, 2007, P. 17
18 Our Method Leading to SSTA (a) (c) Raw silicon RC corner data Raw silicon BEOL process parameter variations data 3σ variations of BEOL process parameters (b) RC corners for comprehensive BEOL structures using Monte-Carlo Method Spread OK? N Validated 3σ corners of BEOL for SSTA Y Jan. 23, 2007, P. 18
19 Validating Corners for SSTA VLSI/SoC designs Layout parameter extraction Validated technologydependent 3σ process profile variation corner data SSTA Jan. 23, 2007, P. 19
20 Conclusion Successful Monte-Carlo Guided RC Simulations help revise RC corners for sparse and wide metals New high-throughput servers help the MCGRC performance and help save test chip designs and costs Extracted random variations can be used for SSTA for DFM. Jan. 23, 2007, P. 20
21 References [1] K. Chang, Accurate onchip variation modeling to achieve design for manufacturability. Proc. 4th IEEE IWSOC, Banff, [2] J. Xiong et al., Robust extraction of spatial correlation, Proc. IEEE ISPD, San Jose, [3] S. Sankaran et al., A 45 nm CMOS node Cu/Lowk/Ultra Low-k PECVD SiCOH (k=2.4) BEOL technology, Proc. IEEE IEDM, San Francisco, [4] TSMC, Foundry Watch, Hsinchu, April Jan. 23, 2007, P. 21
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