Source: Nanju Na Jean Audet David R Stauffer IBM Systems and Technology Group

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1 Title: Package Model Proposal Source: Nanju Na Jean Audet David R Stauffer (dstauffe@us.ibm.com) Date: Dec 27 IBM Systems and Technology Group Abstract: New package models are proposed to represent package responses of real world industry packages available for high speed applications today and to reflect realistic package behavior Package Model Proposal Dec 27

2 Agenda High speed packaging and modeling challenges Package behaviors in measured S-parameters Package behavior in existing IEEE package models 3D EM modeling of package structures New models proposed

3 High speed packaging and modeling challenges Greater impact of high frequency package behavior on signal integrity of Multi- Gbps and up Various discontinuity components exist in package signal path and impact package behavior at high frequencies Using real world package model with high frequency well characterized is critical to reasonable channel analysis and realization 3D package modeling vital to capturing accurate high frequency behavior Manufacturing process and environmental factors to high frequency performance Process variation; impedance tolerance Surface roughness higher loss at high frequencies Material loss higher loss factor at high frequencies Temperature/humidity effect on high frequency loss Design factors for performance as cost-performance tradeoff Design development for high frequency performance improvement Signal behavior is affected by wiring scheme associated with wiring density Impedance control along discontinuity paths

4 Packaging for ASIC high speed applications Cost-performance as primary factor for package selection in average ASIC networking market space Increasing bandwidth demand: link density to noise isolation Package size-layer count versus loss-coupling Organic laminates are prevailingly popular with its cost-performance effectiveness matured technology Various with layer build-up construction technologies; thin core/thick core/coreless limited layer count but high wiring density per layer enabled by low dielectric constant with manufacturing technology advancement Relatively lossy material Ceramic matured technology Excellent reliability and low loss material Poor cost-performance competitiveness Shrinking application space Other packaging developments for general ASIC networking applications Process/material NOT developed or matured to make performance leap in any visible future

5 Package high frequency behavior characterized in measured S-parameters and TDR waveforms -Measurements on actual product packages of a high speed link application -Compared with existing IEEE package models for real package responses

6 Insertion loss measured on 35mm packages [db] [db] Design factor to performance Organic laminate Ceramic [db] Glass Ceramic [GHz] [GHz] [GHz] Differential insertion loss displayed Various design nets measured in each package Transmission varies with trace length, routing via configuration and reflection of the structure (next slide)

7 Return loss measured on 35mm packages [db] [db] Organic laminate Ceramic [GHz] [GHz] [db] Glass Ceramic [GHz] Differential return loss displayed Reflection pattern differs with routing paths/configurations in each package

8 Package discontinuities in measured TDR waveforms [Ω] [Ω] Probing on board pads Probing on board pads C4 pads open C4 pads open Package-board interface (BGA) BGA [Ω] Probing on C4 pads [Ω] Probing on C4 pads Board pads open Board pads open

9 Existing IEEE package models Lossless transmission line?? *product packages are lossy.

10 Non-representative package behavior of IEEE models [db] [db] Too small loss or Unrealistically large reflection bounces Ind-like pkg Differential insertion loss Ind-like pkg Cap-like pkg Cap-like pkg [GHz] Too high reflection in both Modeled using lossless transmission lines (??) while physical packages are lossy. Extremely exotic behavior of inductorlike package model which is not plausible in real packages. Too high return loss in both models Differential TDR waveform of Caplike model, probed from PWB pins Non-real package behavior -4-5 Differential return loss 6 4 Silicon side pins terminated with 5Ωs [GHz] [ps]

11 3D electromagnetic modeling can capture high frequency behavior of package physical structures with multiple discontinuities

12 Typical signal path in organic flip-chip BGA packages consists of multiple discontinuities C4 Buildup via Jogging trace Buildup via Jogging trace Trace (controlled impedance) Manufacturing variation PTH via Buildup via capacitive Solder ball capacitive Buildup vias, jogs Each transition introduces large or small discontinuity and adds reflection and loss PTH vias Solder ball pair Trace differential pair BGA C4

13 3D EM modeling captures high frequency behavior of physical structures OTX_B64T_OUT1

14 Package loss increases with size: 23/35/42/55mm Up to 55mm by JEDEC standard for BGA package Longer interconnect assumed for larger package size Return loss from BGA Trace impedance -5 1Ω Insertion loss 23mm mm 42mm 55mm Trace impedance Ω

15 Performance varies with design and physical layer construction Differential return loss Thick core* PTH via routing under die Thin core Trace impedance 1Ω -4-5 Differential insertion loss 55mm package Trace impedance 115Ω

16 Performance varies with routing scheme/design strategy There is design trade-off in wiring density-performance High performance design option is preferable for high speed data transmission. (1) Small PTH via pitch under die (2) Small PTH via pitch above BGA Chip pads Chip pads Solder balls Solder balls Differential insertion loss (3) PTH vias aligned with BGA [db] (2) Chip pads (1) (3) Solder balls Ref: Nanju Na et. al., Discontinuity impacts and design considerations of high speed differential signals in FC-PBGA packages with high wiring density, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp , Austin, Texas, Oct , 25.

17 Impedance tolerance 15% is achievable Design target impedance of differential pairs is 1Ω. 4 2!15% impedance variation after manufacturing is manageable with current packaging technology 85Ω to 115Ω at 3σ distribution Line Shape Line width +/- X μm Line thickness +/- Y μm Dielectric thickness +/- Z μm 3σ statistics Impedance distribution in measured TDR waveforms Ref: Jean Audet et. al, Manufacturing Impedance Tolerance Control for High Speed Data Link Applications, IEEE 56th Electronic Components and Technology Conference, pp , 26.

18 Package coupling cannot be ignored in moderate to high density packages and needs to be considered in channel analysis

19 Package coupling as part of package behavior Wiring density-isolation is an ASIC cost-performance factor PTH via/ BGA coupling factor to BGA assignments -package size Trace coupling involved in moderate to high package wiring density, moderately manageable Ref: Nanju Na, et. al., Design Optimization for Isolation in High Wiring Density Packages with High Speed SerDes Links, IEEE 56th Electronic Components and Technology Conference, pp , San Diego, Cal. May 3-June 2, 26.

20 Measured near-end crosstalk in high density packages Probed on chip pads of two neighboring pairs with solder balls open -2-2 db(s(1,1)) db(s(1,2)) Near-end pair to pair differential coupling Coupling controlled in design db(s(1,1)) db(s(1,2)) High coupling seen in a high density Ceramic db(s(1,1)) db(s(1,2)) -4-6 db(s(1,1)) db(s(1,2))

21 Package model proposal -Organic flip-chip package modeled as a representative package cost-performance effective and readily available with matured technology most popular in SerDes application space performance comparable among different organic package types design routing option for better transmission -Size: 23mm/55mm (as max. specified by JEDEC) -Impedance tolerance!15% for packaging industry reality -Coupling consideration for reasonable ASIC wiring density

22 Package model #1: Pkg55mm_T33mm115ohm_highBGAcoupling.s8p 55mm package: JEDEC standard maximum 33mm trace (considered longest) with 15% impedance tolerance consideration High BGA coupling HFSS model: PTH vias/bga balls HFSS model: 33mm, Zd=115Ω, Pair coupling -35dB HFSS model: extracted C4 escape

23 Differential pair behavior of the proposed model #1 [db] [db] -1 Insertion loss -1 Return loss [db] Far-end crosstalk -5 [db] Near-end crosstalk

24 Package model #2: Pkg55mm_T33mm115ohm_lowBGAcoupling.s8p 55mm package: JEDEC standard maximum 33mm trace (considered longest) with 15% impedance tolerance consideration Low BGA coupling HFSS model: PTH vias/bga balls HFSS model: 33mm, Zd=115Ω, Pair coupling -35dB HFSS model: extracted C4 escape

25 Package model #3: Pkg35mm_T21mm115ohm_highBGAcoupling.s8p 35mm package 21mm trace (considered longest) with 15% impedance tolerance consideration High BGA coupling HFSS model: PTH vias/bga balls HFSS model: 21mm, Zd=115Ω, Pair coupling -35dB HFSS model: extracted C4 escape

26 Package model #4: Pkg35mm_T21mm115ohm_lowBGAcoupling.s8p 35mm package: JEDEC standard maximum 21mm trace (considered longest) with 15% impedance tolerance consideration Low BGA coupling HFSS model: PTH vias/bga balls HFSS model: 21mm, Zd=115Ω, Pair coupling -35dB HFSS model: extracted C4 escape

27 Back-up

28 Probing for package net measurements

29 OIF Forum: Technical and MA&E Committees Meeting, Nov 6-8, 27 Major design-performance components in organic laminates Trace Electrically long significant impact if not controlled well Impedance control with manufacturing tolerance Design for impedance vs coupling in die escaping region PTH vias Relatively large discontinuity path along vertical signal transition through high dielectric core Impedance effect of via hole/land/pitch Coupling effect with various pair patterns C4 bumps Core BGA Very low impedance and high coupling path due to large geometric volume of the structure interacting with surrounding power/ground I/O assignment pattern for isolation Solder balls

30 Simulation to measurement correlation [GHz] [GHz] Red: simulation Blue: measurement, includes 3mm board microstrip Top left: return loss from C4 pads Top right: return loss from BGAs Bottom: insertion loss [GHz]

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