Modeling and CAD Challenges for DFY. Patrick G. Drennan Freescale Semiconductor Tempe, AZ, USA

Transcription

1 Modeling and CAD Challenges for DFY Patrick G. Drennan Freescale Semiconductor Tempe, AZ, USA

2 Outline Unphysical casing and statistical models Process gradients Gate protect diodes Shallow trench isolation (STI) stress Well proximity Device rotations Metal effects (routing and dummy) Summary Slide 2

3 What Causes Local Variation? Poly/metal grain edge L eff1 > L eff2 dielectric composition and thickness dopant placement and clustering contact quality gate oxide defects emitter contact many others Slide 3

4 What Causes Local Variation? Perimeter σ L2 α 1/W L i L k σ W2 α 1/L Area σ t ox2 α 1/LW σ Leff 1 σ Leff 1 > σ Leff2 Slide 4

5 Local versus Global Local Global L eff1 > L eff2 L eff1 > L eff2 Geometry dependent Geometry independent Lot-to-lot variation Wafer-to-wafer variation Systematic gradients Slide 5

6 4 Perspectives on Variation Components Global Local Correlated Uncorrelated Interdie Intradie Not matched Matched Slide 6

7 Correlated and Uncorrelated Components of Variation Mismatch dominates for for small small geometries Best-case, worst-case analysis for for digital design is is wrong! Slide 7

8 3 Perspectives on Mismatch Data: Difrenza, et al, Proc IEEE ICMTS Model: McAndrew & Drennan, Nanotech 2002 Slide 8

9 Gradients in the Presence of Local Variation Slide 9

10 Gradients Slide 10

11 Confounding of Gradients & Local Variation Gradients can can and and are are reflected in in both both the the expectation (mean, median) and and dispersion (standard deviation) estimates of of the the mismatch distribution. A statistically significant mean mean or or median can can only only come come from from gradient effect effect Slide 11

12 Gradients Slide 12

13 Gradients Several different types Process Temperature Stress (i.e. package) What looks like gradients locally, looks like global variation macroscopically noted exception: ACLV / AFLV. Separate gradients (magnitude & direction) for each process parameter. Slide 13

14 ACLV / AFLV Across Chip Linewidth Variation Across Field Linewidth Variation Repeated trend from chip-to-chip Systematic variation/deviation across chip Not detected by traditional process monitor Step & Scan lithography Mask generation errors Slide 14

15 Putting the Pieces Together shown shown as as linear, linear, but but almost almost always always contains contains nonlinear nonlinear components ACLV Gradient Local variation Slide 15 Total variation (not including LtL WtW var.)

16 What s wrong with this picture? Slide 16

17 What s wrong with this picture? (hint: turn off Metal 3) Slide 17

18 Field Oxide (Shallow Trench Isolation) Stress Slide 18

19 Field Oxide (Shallow Trench Isolation) Stress Id Mismatch Mean(Id1) SD(Idmm) Split active Shared active Id1 (A) 5.00E E E E E E E E E E E+00 Split active Shared active Vgs (V) Vg (V) % Diff in MM b/t shared and split active %Diff in Mean(Id) b/t shared and split active % Diff 300 % Diff Vgs (V) Vgs (V) Slide 19

20 Well Proximity Photoresist STI STI pwell STI n+ p+ STI n+ p+ pwell n+ Slide 20

21 Device Orientation This is what you draw D 1 S S D 2 This is what you get on an older technologies (>0.5um) D 1 S S D 2 Wafer Wafer is is tilted tilted at at 7 degrees degrees during during S/D S/D implant implant to to avoid avoid channeling This is what you get on recent technologies (<0.18um) & it gets worse as the technology gets smaller n+ D 1 S S D 2 p+ p+ n+ n+ substrate = p- Pocket Pocket or or halo halo dopant dopantis is implanted implanted at at an an angle angle in in mult. mult. directions. directions. Halo Halo I/I I/I sets sets Vt. Vt. Small Small change change in in halo halo I/I I/I big big change change in in device. device. Slide 21

22 Metal Routing & Metal Tiling (aka Dummies) Why? Need/want to route metal over devices (esp. large banks) Dummy metals placed to achieve uniform density of dielectric and metal during CMP What? Parasitic capacitances Al metal affects underlying devices H. P. Tuinhout, et al, Proc IEEE IEDM Poly resistors and MOSFETs are affected most Two mechanisms Mechanical stress Local modification of the anneal conditions > Metal blocks N2H2 (forming gas) anneal used in latter stages of process flow > Al by itself, is unstable Wants to oxidize (2Al + 3H 2 O => Al 2 O 3 + 6H) Free H produces locally enhanced anneal Higher level metals have less impact Lower density metal has less impact M1-M3 tiles Slide 22

23 Metal Routing & Metal Tiling (aka Dummies) Al Deposit and Etch Cu Damascene Start at some inter-layer dielectric (ILD) above substrate ILD ILD Start at some inter-layer dielectric (ILD) above substrate Deposit & pattern Al ILD ILD Pattern and etch metal route and vias Deposit new layer of ILD ILD Cu ILD Deposit Cu over entire wafer Etch back new ILD in chemical planarization process ILD ILD Cu Via Use Chemical / Mechanical Polishing (CMP) to remove unwanted Cu Slide 23

24 Summary Impact Modeling CAD Statistics All MOSFETs Models based local & global variation New casing & statistical simulation approach Gradients All devices Location dependant models Back annotation of coordinates from layout to schematic GPD s Offsets in matched MOSFETs Digitally motivated antenna ratios not applicable to analog Check for GPD connected in metal 1 STI stress Non-unity ratios. Shared active vs split aa. Parameters added to compact models Extraction of active area shape & size Well Proximity All MOSFETs Parameters added to compact models Extraction of well edge shape, size & proximity Device rotations Critically timed digital. Matched analog Rotation/mirror dependant models Already exists Metal proximity Matched analog How close is too close? How big the metal? Which metal layers? RC extraction & keepout regions Slide 24

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