Digital Integrated Circuits EECS 312
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1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS dickrp@umich.edu Phone: Cellphone: GSI: Office: Shengshou Lu 2725 BBB luss@umich.edu HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9
2 Review Device trends 1 Explain each transistor operating region. 2 What is pinch-off? 3 How does body bias work? 4 What is velocity saturation? 5 What is sub-threshold operation? 2 Robert Dick Digital Integrated Circuits
3 Lecture plan 1. Device trends Robert Dick Digital Integrated Circuits
4 Process variation Given our current knowledge of transistor operation, what impact will variation in have? dopant concentrations, oxide thickness, transistor width, and interconnect width 4 Robert Dick Digital Integrated Circuits
5 FinFETs Device trends From Freescale. 5 Robert Dick Digital Integrated Circuits
6 Carbon nanotubes and nanowires From AIST. 6 Robert Dick Digital Integrated Circuits
7 Quantum cellular automata Binary information encoded in device configuration. Signals are propagated through nearest neighbor interaction. From Professor Xiaobo Sharon Hu.
8 Quantum cellular automata arithmetic-logic unit From Professor Xiaobo Sharon Hu. 8 Robert Dick Digital Integrated Circuits
9 Single-electron tunneling transistors Source (S) Insulator Gate (G) Island Optional second gate (G2) Junctions Drain (D) 9 Robert Dick Digital Integrated Circuits
10 Common problems Difficult to get high-quality devices where they are needed. High susceptibility to thermal noise. High susceptibility to charge trap offsets. Low gain. 10 Robert Dick Digital Integrated Circuits
11 What does the future hold CMOS for another decade or so, until devices consist of a small integer number of atoms. Nobody knows what comes next. Nothing? New device technology? Implications for information technology? 11 Robert Dick Digital Integrated Circuits
12 Lecture plan 1. Device trends Robert Dick Digital Integrated Circuits
13 Review Device trends 1 List a few different alternatives to CMOS for use in digital systems. 2 Indicate their advantages and disadvantages relative to CMOS. 13 Robert Dick Digital Integrated Circuits
14 NMOSFET 14 Robert Dick Digital Integrated Circuits
15 Insulator properties Low-κ: reduced capacitance, useful for isolating wires. High-κ: increased capacitance, useful for maintaining k despite increased gate thickness. 15 Robert Dick Digital Integrated Circuits
16 High-level fabrication process overview 16 Robert Dick Digital Integrated Circuits
17 Schematic of circuit to fabricate 17 Robert Dick Digital Integrated Circuits
18 Layout of circuit to fabricate 18 Robert Dick Digital Integrated Circuits
19 Overview of fabrication process 19 Robert Dick Digital Integrated Circuits
20 process details From Richard C. Jaeger. Introduction to Microelectronic. Addison-Wesley, 1993.
21 SiO 2 patterning 21 Robert Dick Digital Integrated Circuits
22 Etching Device trends From Richard C. Jaeger. Introduction to Microelectronic. Addison-Wesley, Robert Dick Digital Integrated Circuits
23 Summary of processing steps 1 Define active areas. 2 Etch and fill trenches. 3 Implant well regions. 4 Deposit and pattern polysilicon/metal gate layer. 5 Implant source and drain regions, and substrate contacts. 6 Create contacts and via windows. 7 Deposit and pattern metal layers. 23 Robert Dick Digital Integrated Circuits
24 Step 1: epitaxial layer 24 Robert Dick Digital Integrated Circuits
25 Step 2: gate oxide and sacrificial nitride layer deposition 25 Robert Dick Digital Integrated Circuits
26 Step 3: plasma etching 26 Robert Dick Digital Integrated Circuits
27 Step 4: trench filling, CMP, etching, SiO 2 deposition 27 Robert Dick Digital Integrated Circuits
28 Step 5: n-well and V Tn adjustment implants 28 Robert Dick Digital Integrated Circuits
29 Step 6: p-well and V Tp adjustment implants 29 Robert Dick Digital Integrated Circuits
30 Step 7: polysilicon/metal deposition and etch 30 Robert Dick Digital Integrated Circuits
31 Step 8: n + and p + source, drain, and poly implantation 31 Robert Dick Digital Integrated Circuits
32 Step 9: SiO 2 deposition and contact etch 32 Robert Dick Digital Integrated Circuits
33 Step 10: deposit and pattern first interconnect layer 33 Robert Dick Digital Integrated Circuits
34 Step 11: deposit SiO 2, etch contacts, deposit and pattern second interconnect layer 34 Robert Dick Digital Integrated Circuits
35 Interconnect layers 35 Robert Dick Digital Integrated Circuits
36 Al vs. Cu Device trends For Al, can deposit and etch metal layers. Cu alloys with Si. Cannot safely deposit Cu directly on Si. Cu difficult to controllably etch. Instead, build SiO 2 shield and etch contact regions. 36 Robert Dick Digital Integrated Circuits
37 Damascene process From IBM. 37 Robert Dick Digital Integrated Circuits
38 Device trends Interconnect layers 38 Robert Dick Digital Integrated Circuits
39 Lecture plan 1. Device trends Robert Dick Digital Integrated Circuits
40 Layout production Must define 2-D structure for each mask/layer. Initial topology planning often done. Can be partially or fully automated. Must adhere to design rules. 40 Robert Dick Digital Integrated Circuits
41 Stick diagrams 41 Robert Dick Digital Integrated Circuits
42 Faults and variation Clearly cannot have two wires crossing each other. Variation imposes further constraints. 42 Robert Dick Digital Integrated Circuits
43 Possible faults V DD V DD a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
44 Possible faults V DD V DD a b z a b z V SS bridging fault 43 Robert Dick Digital Integrated Circuits
45 Possible faults V DD V DD a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
46 Possible faults V DD V DD stuck open fault a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
47 Possible faults V DD V DD a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
48 Possible faults V DD V DD stuck at fault a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
49 Possible faults V DD V DD a b z a b z V SS 43 Robert Dick Digital Integrated Circuits
50 Design rules Summary Automatically-checked layout rules. Reduce fault probabilities. Generally regarded as necessary. Caveats Recent studies show many rules are not beneficial. Interaction range is increasing relative to λ. Complicates design rules, making manual comprehension difficult. Design rule checking can be slow. 44 Robert Dick Digital Integrated Circuits
51 Meanings of colors in layouts 45 Robert Dick Digital Integrated Circuits
52 Layout layers 46 Robert Dick Digital Integrated Circuits
53 Intra-layer design rules 47 Robert Dick Digital Integrated Circuits
54 Via design rules 48 Robert Dick Digital Integrated Circuits
55 Layout editor 49 Robert Dick Digital Integrated Circuits
56 Design rule checker 50 Robert Dick Digital Integrated Circuits
57 Lecture plan 1. Device trends Robert Dick Digital Integrated Circuits
58 Packaging requirements Electrical: Good insulators and conductors. Mechanical: Reliable, doesn t stress IC. Thermal: Low thermal resistance to ambient. In some cases, consistency more important. Cost. 52 Robert Dick Digital Integrated Circuits
59 Wire bonding 53 Robert Dick Digital Integrated Circuits
60 Tape automated bonding 54 Robert Dick Digital Integrated Circuits
61 Tape automated bonding die attachment 55 Robert Dick Digital Integrated Circuits
62 Flip-chip bonding 56 Robert Dick Digital Integrated Circuits
63 Through-hole PCB mounting 57 Robert Dick Digital Integrated Circuits
64 Surface mount 58 Robert Dick Digital Integrated Circuits
65 Device trends Example package types 59 Robert Dick Digital Integrated Circuits
66 Chip cap Device trends 60 Robert Dick Digital Integrated Circuits
67 Device trends Heat pipe 61 Robert Dick Digital Integrated Circuits
68 Heat pipe details 62 Robert Dick Digital Integrated Circuits
69 Example of variation in package parameters Type C (pf) L (nh) 68-pin plastic DIP pin ceramic DIP pin PGA 5 15 Wire bond 1 1 Solder bump Robert Dick Digital Integrated Circuits
70 System-on-chip Instead of integrating more ICs, put more on an IC. Advantages: Lower cost per device, compact. Disadvantages: Requires integration of devices fabricated with different processes. 64 Robert Dick Digital Integrated Circuits
71 Move from lead solder Tin lead solder was commonly used. Lead is toxic, accumulates in the body, and is difficult to dispose of. Pure tin works in the short term. May be acceptable as solder in the long term. Problems with plating. 65 Robert Dick Digital Integrated Circuits
72 Tin whiskers Screw dislocations, primarily caused by plating. 66 Robert Dick Digital Integrated Circuits
73 Multi-chip modules Better C than board-level integration. Integrate multiple processes. Somewhat compact. Expensive. 67 Robert Dick Digital Integrated Circuits
74 Multiple active layer 3-D integration Heat sink Silicon layer Carrier layer PCB layer 2-D chip-multiprocessor 3-D chip-multiprocessor Potential for thermal problems. 68 Robert Dick Digital Integrated Circuits
75 Heterogeneous system 3-D integration Integrate Logic. Memory. Analog. Research on discrete components (with soldering). 69 Robert Dick Digital Integrated Circuits
76 Microchannel cooling Credit to David Atienza at EPFL. 70 Robert Dick Digital Integrated Circuits
77 Vapor-phase cooling Credit to Michael J. Ellsworth, Jr. and Robert E. Simons at IBM. 71 Robert Dick Digital Integrated Circuits
78 Summary Device trends CMOS is the most economical way to build digital logic now, but potential alternatives being developed. process is essentially repeated deposition, masking, etching, and polishing steps to dope and build material layers. Al Cu. SiO 2 High-κ and Low-κ. Cu interconnects use damascene process. Poly-Si metal. 72 Robert Dick Digital Integrated Circuits
79 Upcoming topics MOSFET dynamic behavior. Wires. CMOS inverters. 73 Robert Dick Digital Integrated Circuits
80 Lecture plan 1. Device trends Robert Dick Digital Integrated Circuits
81 assignment 24 September: Read Mark T. Bohr, Robert S. Chau, Tahir Ghani, and Kaizad Mistry. The High-k Solution. IEEE Spectrum, October September: 1. 3 October: Lab Robert Dick Digital Integrated Circuits
Digital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
Digital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
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