18-Mar-08. Lecture 5, Transistor matching and good layout techniques

Transcription

1 Transistor mismatch & Layout techniques 1. Transistor mismatch its causes and how to estimate its magnitude 2. Layout techniques for good matching 3. Layout techniques to minimize parasitic effects Part 1: Device Matching (especially transistor matching) Neuromorphic Engineering 2 Spring 08 Delbruck/Indiveri/Liu Transistor matching data From Brad Minch, formerly Cornell, now at Olin Tech Teresa Serrano-Gotarredona, Bernabe Linares-Barranco Inst. of Microelectronics, Sevilla, Spain Statistical rule for matching (aka Pelgrom s rule) Zero order rule: (X is some quantity like V T ) AΔ X σ ( X ) = WL 1. The variance goes as 1/area, i.e., σ goes as 1/dimension 2. Only applies for local, identically-drawn neighbors. 3. There are many refinements to account for spatial locality, large scale effects (tilt), etc. 4. Statistical transistor models try to model individual parameter variations, e.g. V T, β, κ, W/L Small transistors Big mismatch (Inter-die) 1. All devices follow area rule 2. Caps match 1-2 decades better than FETs 3. pfets match worse than nfets (usually) Notes: Gradient and border effects are removed here. I 0 exp(-v T ) and VT has normal distribution JSSC, 39:1, 2004 p Gyvez, Tuinhout,, 1

2 Dominant cause of FET mismatch is random dopant fluctuation Magnitude of V T mismatch Cheng, Roy, Asenov ESSCIRC 2003 AV T σ ( VT) =, what is AV? T WL A VT is reported to be ~1 mv*um per nm oxide thickness (JSSC, 39:1, 2004 p ) Example: 0.35um process with T ox =7nm, A VT =7mV*um. FET with W=L=2um (With λ=0.2um, this is 10/10 λ), σ(v T )=7mV*um/sqrt(2um*2um)=3.5mV Minch measured value is 2.4mV Weak inversion mismatch σ ( ) V T Mismatch is almost constant in weak inversion 0.35u process σ (log I ds ) To zero order, weak inversion mismatch goes as σ ( I ) σ ( VT ) ds = σ (log Ids ) = exp Ids UT It is reported that weak inversion (sometimes) has additional mismatch not accounted for by σ(v T ) I ds I ds Serrano-Gotarredeno, Linares-Barranco 2000 Mismatch process scaling I 0 Reducing mismatch by design Objectives: Good event-threshold uniformity Fast response under wide illumination range I 0 1. From 1.2u to 0.35u, FETs with same λ dim have same mismatch. (not true for deeper submicron, gets worse). 2. Cap matching depends on absolute size. ΔlogI A random variation, 2

3 Use unit devices: e.g. for capacitor matching Part 2: Layout for good device matching e.g. 3:1 capacitor ratio Not very precise Much better (if you can afford it) Put devices as nearby as possible E.g. Matching resistors Use same orientation: e.g. diff pair/current mirror Use common-centroid to cancel gradients: e.g. diff pair with common centroid transistors better Even better: 1. Use dummy devices on ends 2. Use common centroid, 3

4 Surroundings affect matching Use dummy devices to create identical local surroundings Relative capacitance Minch et al. ISCAS 1996 Checklist of Matching Techniques 1. Same dimensions 2. Same structure (do not match nfets with pfets) 3. As large as possible 4. Close to one another 5. Same orientation 6. Laid out in a common-centroid arrangement 7. Surrounding circuits should be similar 8. Same temperature Part 2: General Layout Techniques for Good Performance Every node has a parasitic capacitance and resistance Layout of mixed analog and digital circuits should be carefully planned to minimize parasitic effects and undesirable coupling Digital circuits should have their own power supply lines. Digital ground should not be connected to the substrate! Latchup: avoid it by using lots of substrate and well contacts, 4

5 Shielding from substrate noise Digital circuit Analog circuit Never connect digital ground to the substrate V=LdI/dt noise on digital ground yanks around local substrate. This can move backgate on analog FETs, severely affecting them. Shielding from minority carriers Lab exercise LVS Layout vs. Schematic Steps for LVS exercise 1. Draw schematic/simulate 2. Draw layout 3. Extract schematic and layout to SPICE netlist 4. Run LVS tool to compare netlists 5. Interpret output to spot differences 6. Fix layout (or maybe schematic) iterate to 3. Note: LVS has many options, e.g. check transistor geometry, check R & C values, collapse stacked logic you need to make sure you are using reasonable options Papers about transistor mismatch 1. Lakshmikumar, K.R. Hadaway, R.A. Copeland, M.A. Characterisation and modeling of mismatch in MOS transistors for precision analog design, IEEE J. Solid-State Circuits 1986, 21:6, p M. J. M. Pelgrom, A. C. J. Duinmaiger, and A. P. G. Welbers, Matching properties of MOS transistors for precision analog design, IEEE J. Solid-State Circuits, vol. 24, pp , Oct Aleksandra Pavasovi, Andreas G. Andreou and Charles R. Westgate, Characterization of subthreshold MOS mismatch in transistors for VLSI systems, Analog Int. Circuits and Signal Processing, 1994, 6:1, p Forti, F. Wright, M.E. Measurement of MOS current mismatch in the weak inversion region, IEEE J. Solid- State Circuits 1994, 29:2, p T. Mizuno, J. Okamura, A. Toriumi, "Experimental Study of Threshold Voltage Fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. ED-41, pp , Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "A New 5-Parameter MOS Transistor Mismatch Model," IEEE Electron Device Letters, vol. 21, No. 1, pp January (PDF 144K, 3 pages) 7. Teresa Serrano-Gotarredona and Bernabé Linares-Barranco, "Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation," Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, December (PDF 1.4M, 26 pages) 8. T. Serrano-Gotarredona and B. Linares-Barranco, "A 5-Parameters Mismatch Model for Short Channel MOS Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp , (PDF 266K, 4 pages) 9. The matching of small capacitors for analog VLSI, Minch et. Al. ISCAS 1996 p , 5