Analog IC Design 2010
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1 Analog IC Design 2010 Lecture 7 CAD tools, Simulation and layout Markus Törmänen Markus.Tormanen@eit.lth.se All images are taken from Gray, Hurst, Lewis, Meyer, 5th ed., unless noted otherwise.
2 Contents Simulation: Netlist Transistor models Process corners Example Layout: Design rules Comparing layout and schematic
3 Simulation - Netlist Netlist and schematic Component models Source: Johns & Martin, Analog Integrated Circuit Design
4 Simulation transistor model Transistor models: BSIM3, BSIM4 EKV MM9, MM11 Challenges: How to model the transition between the different regions? Capacitances Output resistance Short channel effects Mobility degradation Velocity saturation Geometry dependent parameters Mobility Temperature dependence Source: B. Razavi, Design of Analog CMOS Integrated Circuits
5 BSIM- model Example: threshold voltage Long-channel, uniform doping: V th = VTH0 + γ( (Φs-V bs ) - Φs) Non-uniform doping: V th = VTH0 + K1( (Φs-V bs ) - Φs) K2V bs
6 BSIM - Summary The model is: Physics based - some fitting parameters Accurate Scalable > 100 parameters BSIM: ~bsim3/bsim4.html
7 Simulation process corners How do we take into account process variations? Lot to lot Wafer to wafer Die to die These variations are translated to speed variations Typical Slow Fast Source: B. Razavi, Design of Analog CMOS Integrated Circuits
8 Simulation - Example Amplifier: 2-stage Opamp
9 Simulation - Example Simulations: DC, time domain, frequency domain, noise, RF, Example: Opamp in negative feedback configuration A v = v o /v i = kΩ/10kΩ = 10
10 Simulation - Example Non-inverting amplifier with differentiator v o /v i (s) = 1 + R 1 / Z C = 1 + scr 1
11 Simulation - Example Open-loop opamp: Frequency response Amplitude Phase
12 Simulation - Example Amplifier in unity gain: Step response time domain
13 Simulation - Example Amplifier in unity gain, AC simulation: Linearized circuit parameters!
14 Simulation - Example Noise simulation: Noise vs frequency Referred to input/output
15 2 minute question! Discuss in groups of 2 or 3 the following questions: What is the fundamental difference between transient and AC simulation? Which one is more time consuming? Be prepared to give a short comment based on your group discussion
16 Layout - Design rules CAD tool: Design rule check E.g. Cadence Assura Example of design rules for a 0.35um CMOS technology: eit/courses/eti063/geometry 035.pdf (see also Course Material)
17 Layout - Comparing layout and schematic LVS: Layout vs schematic Compare netlists Compare device sizes Compare terminals CAD tool: Assura Only after running a succesful LVS the parasitics can be extracted Select Assura > Run RCX to do this Then, the extracted view can be used in post-layout simulations Tool: schematic view config
18 Links General information on Cadence & CADtools: (note that the lab manual precedes over the general information!) Simulator used in this course: GoldenGate Golden gate manuals can be found at '/usr/local-eit/cad2/agilent/goldengate-4-2-0/doc/gg_help.html (Copy link to the browser on a computer in E:2435)
19 Extra - BSIM - manual
20 BSIM - manual
21 BSIM - manual
22 BSIM - manual
23 BSIM - manual
24 BSIM - manual
25 BSIM - manual
26 BSIM - manual
27 BSIM - manual
Analog IC Design 2011
Analog IC Design 2011 Lecture 11 - Fully differential Opamps Markus Törmänen Markus.Tormanen@eit.lth.se All images are taken from Gray, Hurst, Lewis, Meyer, 5th ed., unless noted otherwise. 111010 Markus
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