Wiring Parasitics. Contact Resistance Measurement and Rules

Transcription

1 Wiring Parasitics Contact Resistance Measurement and Rules

2 Connections between metal layers and nonmetal layers are called contacts. Connections between metal layers are called vias. For non-critical design, a simple lumped resistance based on process measurements is substituted. Contact Resistance Parasitic Resistance Extraction (PRE) programs typically model contact resistance as a small network.

3 Contact resistance is a function of layout geometry, the layers contacted, and the particular manufacturing process. Contact resistance is generally considered very low, although it may range from 10 s of mw to 10 s of W. Resistance Magnitude Component Resistance Typical Use metal very low power and signal lines metal2 very low power lines polysilicon low signal lines and transistor gates n-type diffusion medium signal lines and sources and drains of transistors p-type diffusion medium signal lines and sources and drains of transistors contact very low signal connection (routing) via very low signal connection between metal layers (routing)

4 CMOS Joining Rules Typical two-metal-layer process. n-type diffusion p-type diffusion poly metal metal2 -type iffusion T C -type iffusion T C oly etal T T C C C C V etal2 V Symbol Meaning allowed T C V not allowed Transistor formed contact required via required

5 Effects of Contact Resistance Contact resistance is an unwanted feature which must be accounted for in both high speed analog and digital designs. As feature size decreases, the significance of contact resistance contributions to circuit behaviour increases. Propagation delay time can be dominated by contact resistance for 0.1µm m CMOS with ρ c > Ωcm 2

6 Process Evaluation Devices (PEDs) are typically placed on each wafer. Process dependent parameters are monitored using these sacrificial dice. It is important to maximize the usage of these dice. Measuring Contact Resistance PED

7 Meander Contact Chain Typical layout for measuring contact resistance. The metal resistance and the secondary layer (e.g. n-diff) resistance is also included in the measurement. There is an inherent spatial orientation bias. metal contact n-diff, p-diff, p poly

8 The Hilbert Curve The Hilbert-Peano Curve is conveniently described by an L-System L using an initial state of either L or R and the paired transformation rules, L + R F - L F L - F R + R - L F + R F R + F L - (When plotting the curve, the characters L and R are ignored.)

9 Hilbert Contact Chains The Hilbert-Peano Curve algorithm implemented in the layout package generates the contact chain. Hilbert-Peano curve properties reduce spatial orientation bias in the measurements.

10 Layout Rules for Contacts

11 Basic Definitions WIDTH : SPACE : CLEARANCE : EXTENSION : OVERLAP :

12 Reserved Mask Names NW --- Definition of N-Well PW --- Definition of P-Well OD --- Definition of thin oxide for device and interconnection OD2 --- Definition of thick oxide for 5V device PO --- Definition of Poly-1 Si for gate and capacitor bottom plate PO2 --- Definition of Poly-2 Si for resistor and capacitor top plate 3VN --- Definition of NLDD implantation for 3V device 5VN --- Definition of NLDD implantation for 5V device PP --- Definition of P+ implantation NP --- Definition of N+ implantation

13 Reserved Mask Names 3VESD --- Definition of ESD implantation for 3V I/O 5VESD --- Definition of ESD implantation for 5V I/O CO --- Definition of contact window from M1 to OD, PO or PO2 M1 --- Definition of 1st metal for interconnection VIA1 --- Definition of via1 hole between M2 and M1 M2 --- Definition of 2nd metal for interconnection VIA2 --- Definition of via2 hole between M3 and M2 M3 --- Definition of 3rd metal for interconnection VIA3 --- Definition of via1 hole between M4 and M3 M4 --- Definition of 4th metal for interconnection CB --- Definition of bonding pad

14 Contact Rule (156) Rule No. Description Layout Rule Contact Rules Layer : CO --- Contact Window CO.W.1 Minimum and maximum width of a CO region A 0.4 um CO.S.1 Minimum space between two CO regions B 0.4 um CO.C.1 CO.C.2 CO.E.1 CO.E.2 CO.E.3 CO.E.4 CO.R.1 Minimum clearance from a CO on OD region to a PO gate Minimum clearance from a CO on PO region to an OD region Minimum extension of an OD region beyond a CO region Minimum extension of a PO region beyond a CO region Minimum extension of a PP region beyond a CO region Minimum extension of an NP region beyond a CO region, Poly contact on OD area is forbidden C 0.3 um D 0.4 um E 0.15 um F 0.2 um G 0.25 um H 0.25 um CO.R.2 Butted Contact is not allowed. I

15 Contact Rules: Reference Layout E PO OD G PP B CO CO C A N+ PP NP H E D N+ PO E F

16 Typical I/O Pad I/O Pad Structure RF Pad M2 bonding wire M2 bonding wire M1 via M1 substrate substrate M1 & M2 shorted, capacitively coupled to substrate through oxide. Substrate acts as a resistor to ground, fouling matching and adding resistor noise. M1 & M2 capacitively coupled. M1 shorted to ground. M1 shields M2 from substrate. Capacitance can be tuned out by off-chip inductor.