due to power supply and technology. Process specifications were obtained from the MOSIS
|
|
- Cameron Leonard
- 6 years ago
- Views:
Transcription
1 design number VLSI Design Chromatic Instrument Tuner For the design of the operational amplifier, we have to take into consideration the constraints due to power supply and technology. Process specifications were obtained from the MOSIS Integrated Circuit Fabrication Sevice website. Power supply: ±2.5V Technology: C5N: 0.5 µm
2 Also, our desired specifications for our amplifier are: or
3
4
5 If, then, so had to be greater than. A good value for would be. To calculate, slew-rate and are used on the following equation: By using ICMR, the ratio can be calculated by the following equation: microsiemens = µa/v To calculate the ratio And to calculate the ratio
6 has to be greater than, so All these calculations are only to have an idea the values of the MOSFETs in order to get the specifications we need on the op-amp. Regardless, most of the main changes would be made on Cadence by simulations.
7 The following schematic (Figure 1) is the final design of the operational amplifier that will be used in the instrument tuner design. We also show the specifications for the device. Figure 1 or
8 The following waveforms (Figure 2) demonstrate how the op amp performs with an inverting configuration at a gain of -4. The input sine wave is at 250mV pk-pk, and the output inverts at 1V pk-pk. Figure 2
9 The following waveforms (Figure 3) demonstrate how the op amp performs with a non-inverting configuration at a gain of 5. The input sine wave is at 250mV pk-pk, and the output amplifies to 1.25V. Figure 3
10 The following waveforms (Figure 4) demonstrate how the op amp performs with a simple voltage follower configuration. The input sine wave is at 250mV pk-pk, and the output follows to 250mV pk-pk. Figure 5
11 Layout of Resistor Theory The basic formula of resistance is In VLSI (Very-Large-Scale Inyegration), since the thickness of any given layer is fixed, the previous formula can be transformed as: In this equation, w is the width of the resistor, ρ' is resistance per square (sheet resistance), and N is the number of squares. In principle, any layer can be used to construct resistor; however, practically only those layers that have weak conductivity are proper for resistor layout. Practice In the process we are using, there are two layers that we usually use for resistor layout, poly and highres poly2. Poly has a sheet resistance of 25Ω/square which is suitable for resistors under 3kΩ. For resistors over 3kΩ, highres poly2, which has a sheet resistance of 1.2kΩ/square, is used. Highres poly2 is not a physical layer. It represents a doping process on poly2 layer which adds impurities to poly2, thus reduces the conductivity. In order to reduce the layout area, minimum width of poly or poly2 path (0.6µm) is applied.
12 Sample layout of 20kΩ resistor 1. Calculation Note: Round length to the nearest multiple of, 10.05µm. That is, a path of 0.6µm wide and 10.05µm long is needed. 2. Draw poly2 (elec) path 3. Place Contacts Figure 6 Place two M1_ELEC contacts at the two end of the poly2 path. Figure 7
13 4. Draw highres From the LSW (layer selection window) draw a highres rectangle to cover the area between the contacts. 5. Place pins Figure 8 Place POS and NEG metal1 pins on top of the M1_ELEC contacts. Figure 9
14 6. Extraction Do an extraction without any switch. Open the extracted view. A resistor symbol should be placed at the left pin. Check the value to ensure it is what you designed for. Figure 10 In this case, the value you see on the extracted view is not exactly 20kΩ, but within the allowed error range.
15 For our design, we will need a 15KΩ resistor to bias the current mirrors that will power the op amp. Layout Extraction Figure 11 Parameter verification Figure 12
16 Figure 13 Layout of Capacitor Theory In principle, a capacitor is composed of two adjacent conductor plates with certain type of dielectric in between. The capacitance is calculated based on the following formula: as: If d and ε are constants and the area is a rectangle, the previous formula can be modified Therefore, to lay out a capacitor, we have to figure out the geometric parameters of the rectangle based on C and c. Practice In the process C5N_SUBME (λ=0.30µm), the two polysilicon (poly and elec, also known as poly2) are a proper pair to form a capacitor. The thin silicon dioxide between these adjacent layers yields good capacitance value per unit area. This type of capacitor is called poly-poly2 capacitor.
17 Sample layout of 100fF capacitor 1. Calculation Note: Round l to the nearest multiple of ; remember in Cadence, we can only draw geometric lengths of multiple. Consequently, if w is given as 13.89µm, you have to convert it to 13.95µm before you get started. 2. Draw poly and elec layers Draw a 9µm x 13.95µm rectangle with elec (yellow). Then cover it with a poly (red), which should exceed every side of elec (yellow) by 3µm.
18 Figure Cover the elec rectangle with M1_ELEC contacts and a metal1 rectangle. Use as many M1_ELEC contact as possible, without violating DRC, to cover the whole effective capacitance area (elec). Then cover the elec with a metal rectangle. The purpose of these contacts and metal1 is to minimize parasitic resistance.
19 Figure Cover the 3µm extended poly edge with M1_POLY contacts and metal1. Use as many M1_POLY contacts as possible, without violating DRC (design rule check), to cover the extended poly edge. Each M1_POLY is 1.2µm wide and DRC requires 1.8µm between the contact and elec. Then cover the M1_POLY contacts with metal1. The purpose of these contacts is also to minimize parasitic resistance.
20 Figure Draw a n-well to cover the whole capacitor Draw an n-well to cover the poly rectangle with 0.6µm extension to fulfill the DRC requirement. The purpose of this n-well is to minimize field leakage. Figure 17
21 6. Place pins Place a metal2 POS pin and a M2_M1 contact on top of a M1_POLY contact. Place a metal2 NEG pin and a M2_M1 contact on top of a M1_ELEC contact. Of course you can move the pins outside and use metal2 to connect them to the respective contacts. 7. DRC (design rule) check Check DRC, and correct all errors. Figure 18
22 8. Extraction Do an extraction without any switch and open the extracted view. A capacitor symbol should be placed at the upper-left corner of the inner rectangle. Choose the symbol, and check its value to ensure your layout is correct. You are not going to get an exact match since the adjustment we made to fulfill the requirement, but a reasonable error is allowed. Figure 19
23 Our design will require two capacitors: a compensating capacitor that will create a dominant pole for the op amp, and another that will block out the DC voltage at the final, buffer stage. The first one that was laid out the compensating capacitor,. The compensating capacitor was calculated at 3pF. Note: The arbitrary width of 60µm is a factor of. Layout Figure 19
24 Extraction Figure 20 Parameter verification Figure 19
25 The second capacitor that was laid out was the one for the final stage; it was calculated at 500fF, relatively smaller than the previous one. Note: Since the arbitrary width of 25µm is not a factor of, we also have to adjust it to 25.05µm. Layout Figure 20
26 Extraction Figure 21 Parameter verification Figure 22
27 Layout of Operational Amplifier Layout Figure 23
28 Extracted Figure 24
29 LVS: Net-lists match Figure 25
30
31
32
Basic Layout Techniques
Basic Layout Techniques Rahul Shukla Advisor: Jaime Ramirez-Angulo Spring 2005 Mixed Signal VLSI Lab Klipsch School of Electrical and Computer Engineering New Mexico State University Outline Transistor
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationECE4902 B2015 HW Set 1
ECE4902 B2015 HW Set 1 Due in class Tuesday November 3. To make life easier on the graders: Be sure your NAME and ECE MAILBOX NUMBER are prominently displayed on the upper right of what you hand in. When
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationECEN 474/704 Lab 7: Operational Transconductance Amplifiers
ECEN 474/704 Lab 7: Operational Transconductance Amplifiers Objective Design, simulate and layout an operational transconductance amplifier. Introduction The operational transconductance amplifier (OTA)
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationPURPOSE: NOTE: Be sure to record ALL results in your laboratory notebook.
EE4902 Lab 9 CMOS OP-AMP PURPOSE: The purpose of this lab is to measure the closed-loop performance of an op-amp designed from individual MOSFETs. This op-amp, shown in Fig. 9-1, combines all of the major
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture
More informationWhen you have completed this exercise, you will be able to relate the gain and bandwidth of an op amp
Op Amp Fundamentals When you have completed this exercise, you will be able to relate the gain and bandwidth of an op amp In general, the parameters are interactive. However, in this unit, circuit input
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationDesign of High Gain Two stage Op-Amp using 90nm Technology
Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG
More informationChapter 9: Operational Amplifiers
Chapter 9: Operational Amplifiers The Operational Amplifier (or op-amp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,
More informationFUNDAMENTALS OF MODERN VLSI DEVICES
19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution
More informationCMOS Operational Amplifier
The George Washington University Department of Electrical and Computer Engineering Course: ECE218 Instructor: Mona E. Zaghloul Students: Shunping Wang Yiping (Neil) Tsai Data: 05/14/07 Introduction In
More informationDesign of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron
More informationEE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1
EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules
More informationEE301 Electronics I , Fall
EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials
More informationETIN25 Analogue IC Design. Laboratory Manual Lab 2
Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation
More informationECE4902 C Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load
ECE4902 C2012 - Lab 5 MOSFET Common Source Amplifier with Active Load Bandwidth of MOSFET Common Source Amplifier: Resistive Load / Active Load PURPOSE: The primary purpose of this lab is to measure the
More informationDesign and Layout of Two Stage High Bandwidth Operational Amplifier
Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard
More informationDesign Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage
Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Sadeque Reza Khan Department of Electronic and Communication Engineering, National
More informationSticks Diagram & Layout. Part II
Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped
More information10-Bit 5MHz Pipeline A/D Converter. Kannan Sockalingam and Rick Thibodeau
10-Bit 5MHz Pipeline A/D Converter Kannan Sockalingam and Rick Thibodeau July 30, 2002 Contents 1 Introduction 8 1.1 Project Overview........................... 8 1.2 Objective...............................
More informationPrecision Rectifier Circuits
Precision Rectifier Circuits Rectifier circuits are used in the design of power supply circuits. In such applications, the voltage being rectified are usually much greater than the diode voltage drop,
More informationPHYS 536 The Golden Rules of Op Amps. Characteristics of an Ideal Op Amp
PHYS 536 The Golden Rules of Op Amps Introduction The purpose of this experiment is to illustrate the golden rules of negative feedback for a variety of circuits. These concepts permit you to create and
More informationA 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20
A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20 Joseph Adut,Chaitanya Krishna Chava, José Silva-Martínez March 27, 2002 Texas A&M University Analog
More informationv 0 = A (v + - v - ) (1)
UNIVERSITI TEKNOLOGI MALAYSIA KURSUS KEJURUTERAAN ELEKTRIK ELECTRONIC ENGINEERING LABORATORY 2 EXPERIMENT 2 : OPERATIONAL AMPLIFIER PRELIMINARY REPORT Name : Section : Group : Lecturer : Marks : 20 Attach
More informationMicroelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC
Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC F. Xavier Moncunill Autumn 2018 5 Analog integrated circuits Exercise 5.1 This problem aims to follow the steps in the design of
More informationDEPARTMENT OF ELECTRICAL ENGINEERING LAB WORK EE301 ELECTRONIC CIRCUITS
DEPARTMENT OF ELECTRICAL ENGINEERING LAB WORK EE301 ELECTRONIC CIRCUITS EXPERIMENT : 3 TITLE : Operational Amplifier (Op-Amp) OUTCOME : Upon completion of this unit, the student should be able to: 1. Gain
More informationLecture 2: Non-Ideal Amps and Op-Amps
Lecture 2: Non-Ideal Amps and Op-Amps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical Op-Amps Linear Imperfections: Finite open-loop gain (A 0 < ) Finite input resistance
More informationDigital Applications of the Operational Amplifier
Lab Procedure 1. Objective This project will show the versatile operation of an operational amplifier in a voltage comparator (Schmitt Trigger) circuit and a sample and hold circuit. 2. Components Qty
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationFabrication, Corner, Layout, Matching, & etc.
Advanced Analog Building Blocks Fabrication, Corner, Layout, Matching, & etc. Wei SHEN (KIP) 1 Fabrication Steps for MOS Wei SHEN, Universität Heidelberg 2 Fabrication Steps for MOS Wei SHEN, Universität
More informationECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier
ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of
More informationBasic Fabrication Steps
Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 2018 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationDifference between BJTs and FETs. Junction Field Effect Transistors (JFET)
Difference between BJTs and FETs Transistors can be categorized according to their structure, and two of the more commonly known transistor structures, are the BJT and FET. The comparison between BJTs
More informationExperiment 8 Frequency Response
Experiment 8 Frequency Response W.T. Yeung, R.A. Cortina, and R.T. Howe UC Berkeley EE 105 Spring 2005 1.0 Objective This lab will introduce the student to frequency response of circuits. The student will
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationLab 2: Discrete BJT Op-Amps (Part I)
Lab 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and
More informationChapter 9: Operational Amplifiers
Chapter 9: Operational Amplifiers The Operational Amplifier (or op-amp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,
More informationUNIT I. Operational Amplifiers
UNIT I Operational Amplifiers Operational Amplifier: The operational amplifier is a direct-coupled high gain amplifier. It is a versatile multi-terminal device that can be used to amplify dc as well as
More information30 ma flash LDO voltage regulator (output voltage 1.8 ± 0.2 V)
SPECIFICATION 1 FEATURES Global Foundries CMOS 55 nm Low drop out Low current consumption Two modes operations: Normal, Economy Mode operation Bypass No discrete filtering capacitors required (cap-less
More informationELT 215 Operational Amplifiers (LECTURE) Chapter 5
CHAPTER 5 Nonlinear Signal Processing Circuits INTRODUCTION ELT 215 Operational Amplifiers (LECTURE) In this chapter, we shall present several nonlinear circuits using op-amps, which include those situations
More informationElectronics basics for MEMS and Microsensors course
Electronics basics for course, a.a. 2017/2018, M.Sc. in Electronics Engineering Transfer function 2 X(s) T(s) Y(s) T S = Y s X(s) The transfer function of a linear time-invariant (LTI) system is the function
More informationEK307 Active Filters and Steady State Frequency Response
EK307 Active Filters and Steady State Frequency Response Laboratory Goal: To explore the properties of active signal-processing filters Learning Objectives: Active Filters, Op-Amp Filters, Bode plots Suggested
More informationTest Your Understanding
074 Part 2 Analog Electronics EXEISE POBLEM Ex 5.3: For the switched-capacitor circuit in Figure 5.3b), the parameters are: = 30 pf, 2 = 5pF, and F = 2 pf. The clock frequency is 00 khz. Determine the
More informationLow Distortion Design 4
Low Distortion Design 4 TIPL 1324 TI Precision Labs Op Amps Presented by Collin Wells Prepared by John Caldwell Prerequisites: Noise 1 3 (TIPL1311 TIPL1313) Distortion from Power Supplies Power supplies
More information6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
More informationTechnology, Jabalpur, India 1 2
1181 LAYOUT DESIGNING AND OPTIMIZATION TECHNIQUES USED FOR DIFFERENT FULL ADDER TOPOLOGIES ARPAN SINGH RAJPUT 1, RAJESH PARASHAR 2 1 M.Tech. Scholar, 2 Assistant professor, Department of Electronics and
More informationOp-Amp Simulation Part II
Op-Amp Simulation Part II EE/CS 5720/6720 This assignment continues the simulation and characterization of a simple operational amplifier. Turn in a copy of this assignment with answers in the appropriate
More informationCircuit Layout Techniques And Tips (Part III of VI) by Bonnie C. Baker and Ezana Haile, Microchip Technology Inc.
Circuit Layout Techniques And Tips (Part III of VI) by Bonnie C. Baker and Ezana Haile, Microchip Technology Inc. The major classes of parasitic generated by the PC board layout come in the form of resistors,
More informationLow-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier
Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier A dissertation submitted in partial fulfillment of the requirement for the award of degree of Master of Technology in VLSI Design
More informationECEN 325 Lab 5: Operational Amplifiers Part III
ECEN Lab : Operational Amplifiers Part III Objectives The purpose of the lab is to study some of the opamp configurations commonly found in practical applications and also investigate the non-idealities
More informationHomework Assignment 03
Homework Assignment 03 Question 1 (Short Takes), 2 points each unless otherwise noted. 1. Two 0.68 μf capacitors are connected in series across a 10 khz sine wave signal source. The total capacitive reactance
More informationQuestion Paper Code: 21398
Reg. No. : Question Paper Code: 21398 B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2013 Fourth Semester Electrical and Electronics Engineering EE2254 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS (Regulation
More informationSingle Sided and Double Sided Silicon MicroStrip Detector R&D
Single Sided and Double Sided Silicon MicroStrip Detector R&D Tariq Aziz Tata Institute, Mumbai, India SuperBelle, KEK December 10-12, 2008 Indian Effort Mask Design at TIFR, Processing at BEL Single Sided
More informationLow noise Amplifier, simulated and measured.
Low noise Amplifier, simulated and measured. Introduction: As a study project a low noise amplifier shaper for capacitive detectors in AMS 0.6 µm technology is designed and realised. The goal was to design
More informationINTEGRATED CIRCUITS. AN109 Microprocessor-compatible DACs Dec
INTEGRATED CIRCUITS 1988 Dec DAC products are designed to convert a digital code to an analog signal. Since a common source of digital signals is the data bus of a microprocessor, DAC circuits that are
More informationDiscrete Op-Amp Kit MitchElectronics 2019
Discrete Op-Amp Kit MitchElectronics 2019 www.mitchelectronics.co.uk CONTENTS Introduction 3 Schematic 4 How It Works 5 Materials 9 Construction 10 Important Information 11 Page 2 INTRODUCTION Even if
More informationHomework Assignment True or false. For both the inverting and noninverting op-amp configurations, V OS results in
Question 1 (Short Takes), 2 points each. Homework Assignment 02 1. An op-amp has input bias current I B = 1 μa. Make an estimate for the input offset current I OS. Answer. I OS is normally an order of
More informationLab 10: Single Supply Amplifier
Overview This lab assignment implements an inverting voltage amplifier circuit with a single power supply. The amplifier output contains a bias point which is removed by AC coupling the output signal.
More informationMAS.836 HOW TO BIAS AN OP-AMP
MAS.836 HOW TO BIAS AN OP-AMP Op-Amp Circuits: Bias, in an electronic circuit, describes the steady state operating characteristics with no signal being applied. In an op-amp circuit, the operating characteristic
More informationLecture 240 Cascode Op Amps (3/28/10) Page 240-1
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationSolid State Devices- Part- II. Module- IV
Solid State Devices- Part- II Module- IV MOS Capacitor Two terminal MOS device MOS = Metal- Oxide- Semiconductor MOS capacitor - the heart of the MOSFET The MOS capacitor is used to induce charge at the
More informationJames Lunsford HW2 2/7/2017 ECEN 607
James Lunsford HW2 2/7/2017 ECEN 607 Problem 1 Part A Figure 1: Negative Impedance Converter To find the input impedance of the above NIC, we use the following equations: V + Z N V O Z N = I in, V O kr
More informationEE584 (Fall 2006) Introduction to VLSI CAD Project. Design of Ring Oscillator using NOR gates
EE584 (Fall 2006) Introduction to VLSI CAD Project Design of Ring Oscillator using NOR gates By, Veerandra Alluri Vijai Raghunathan Archana Jagarlamudi Gokulnaraiyn Ramaswami Instructor: Dr. Joseph Elias
More informationLMC6032 CMOS Dual Operational Amplifier
LMC6032 CMOS Dual Operational Amplifier General Description The LMC6032 is a CMOS dual operational amplifier which can operate from either a single supply or dual supplies. Its performance features include
More informationExam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage?
Exam 2 Name: Score /90 Question 1 Short Takes 1 point each unless noted otherwise. 1. Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance
More informationIntegrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI
1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationEE 368 Electronics Lab. Experiment 10 Operational Amplifier Applications (2)
EE 368 Electronics Lab Experiment 10 Operational Amplifier Applications (2) 1 Experiment 10 Operational Amplifier Applications (2) Objectives To gain experience with Operational Amplifier (Op-Amp). To
More informationGeorgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam
Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID number
More informationDesign of a low voltage,low drop-out (LDO) voltage cmos regulator
Design of a low,low drop-out (LDO) cmos regulator Chaithra T S Ashwini Abstract- In this paper a low, low drop-out (LDO) regulator design procedure is proposed and implemented using 0.25 micron CMOS process.
More informationLM148/LM248/LM348 Quad 741 Op Amps
Quad 741 Op Amps General Description The LM148 series is a true quad 741. It consists of four independent, high gain, internally compensated, low power operational amplifiers which have been designed to
More informationLMC6081 Precision CMOS Single Operational Amplifier
LMC6081 Precision CMOS Single Operational Amplifier General Description The LMC6081 is a precision low offset voltage operational amplifier, capable of single supply operation. Performance characteristics
More informationMICROWIND2 DSCH2 8. Converters /11/00
8-9 05/11/00 Fig. 8-7. Effect of sampling The effect of sample and hold is illustrated in figure 8-7. When sampling, the transmission gate is turned on so that the sampled data DataOut reaches the value
More informationLPC662 Low Power CMOS Dual Operational Amplifier
LPC662 Low Power CMOS Dual Operational Amplifier General Description The LPC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It features a wide range of operating voltage
More informationDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 019.101 Introductory Analog Electronics Laboratory Laboratory No. READING ASSIGNMENT
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More informationFrequency Response Properties of the Silicon Vertex Detector for BaBar
Frequency Response Properties of the Silicon Vertex Detector for BaBar Lawrence Lin Jeff Richman Sam Burke UCSB Summer 2001 Contents 1 Introduction 2 2 p-side of the Detector 3 3 n-side of the Detector
More informationECE 6770 FINAL PROJECT
ECE 6770 FINAL PROJECT POINT TO POINT COMMUNICATION SYSTEM Submitted By: Omkar Iyer (Omkar_iyer82@yahoo.com) Vamsi K. Mudarapu (m_vamsi_krishna@yahoo.com) MOTIVATION Often in the real world we have situations
More informationRail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta
1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly
More informationExperiment 1: Amplifier Characterization Spring 2019
Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using
More informationLecture 200 Cascode Op Amps - II (2/18/02) Page 200-1
Lecture 200 Cascode Op Amps II (2/18/02) Page 2001 LECTURE 200 CASCODE OP AMPS II (READING: GHLM 443453, AH 293309) Objective The objective of this presentation is: 1.) Develop cascode op amp architectures
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationC H A P T E R 02. Operational Amplifiers
C H A P T E R 02 Operational Amplifiers The Op-amp Figure 2.1 Circuit symbol for the op amp. Figure 2.2 The op amp shown connected to dc power supplies. The Ideal Op-amp 1. Infinite input impedance 2.
More informationLMC6032 CMOS Dual Operational Amplifier
LMC6032 CMOS Dual Operational Amplifier General Description The LMC6032 is a CMOS dual operational amplifier which can operate from either a single supply or dual supplies. Its performance features include
More informationAmplifiers Frequency Response Examples
ECE 5/45 Analog IC Design We will use the following MOSFET parameters for hand-calculations and the µm CMOS models for corresponding simulations. Table : Long-channel MOSFET parameters. Parameter NMOS
More informationDESIGN OF ON CHIP TEMPERATURE MONITORING IN 90NM CMOS
DESIGN OF ON CHIP TEMPERATURE MONITORING IN 90NM CMOS A thesis submitted to the faculty of San Francisco State University In partial fulfillment of The Requirements for The Degree Master of Science In
More informationLM6118/LM6218 Fast Settling Dual Operational Amplifiers
Fast Settling Dual Operational Amplifiers General Description The LM6118/LM6218 are monolithic fast-settling unity-gain-compensated dual operational amplifiers with ±20 ma output drive capability. The
More informationLab 7: DELTA AND SIGMA-DELTA A/D CONVERTERS
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 6 Lab 7: DELTA AND SIGMA-DELTA A/D CONVERTERS Goal The goals of this experiment are: - Verify the operation of a differential ADC; - Find the
More informationVLSI Chip Design Project TSEK06
VLSI Chip Design Project TSEK06 Project Description and Requirement Specification Version 1.1 Project: 100 MHz, 10 dbm direct VCO modulating FM transmitter Project number: 4 Project Group: Name Project
More informationLMC662 CMOS Dual Operational Amplifier
LMC662 CMOS Dual Operational Amplifier General Description The LMC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It operates from +5V to +15V and features rail-to-rail
More informationCS/ECE 5710/6710. Composite Layout
CS/ECE 5710/6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different
More informationCMOS synchronous Buck switching power supply Raheel Sadiq November 28, 2016
CMOS synchronous Buck switching power supply Raheel Sadiq November 28, 2016 Part 1: This part of the project is to lay out a bandgap. We previously built our bandgap in HW #13 which supplied a constant
More informationWiring Parasitics. Contact Resistance Measurement and Rules
Wiring Parasitics Contact Resistance Measurement and Rules Connections between metal layers and nonmetal layers are called contacts. Connections between metal layers are called vias. For non-critical design,
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More information