Accuracy and Speed Performance of HiSIM Versions 231 and 240
|
|
|
- Madeline Meryl Walsh
- 5 years ago
- Views:
Transcription
1 Accuracy and Speed Performance of HiSIM Versions 231 and 240 H.J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake Graduate School of Advanced Sciences of Matter, Hiroshima University T. Iizuka NEC Electronics T. Ohguro Toshiba H. Koike Sony S. Yamaguchi Fujitsu R. Inagaki, Y. Furui Semiconductor Technology Academic Research Center (STARC) MOS-AK Workshop ; 14 September
2 Outline Overview of Compact-Modeling Approaches Accuracy Aspects of HiSIM2.3.1 and Speed Versus Accuracy Trade-Off and Position of Leading Compact Models Conclusion MOS-AK Workshop ; 14 September
3 Basic Compact Model Approaches for the MOSFET Threshold-Voltage-Based Models (e. g. BSIM3, BSIM4) currents expressed as functions of applied voltages different equations for: - sub-threshold region - linear region - saturation region New Generation of Surface-Potential-Based Models implicit equation for surface potential currents determined from drift and diffusion term of current density equation developed calculation methods for the surface potential: - iterative solution with the exact surface-potential equation HiSIM - approximate explicit solution by 1 st & 2 nd order perturbation theory, after prior conditioning of the surface-potential equation New Generation of Inversion-Charge-Based Models additional approximation to solve for inversion charge EKV, BSIM5, AMC PSP MOS-AK Workshop ; 14 September
4 HiSIM Development History 1990 JJAP Sub-1µm MOSFETs short-channel effect model 1991 SISPAD 1 st surface-potential-based model parameter extraction strategy 1994 ICCAD simulation time & stability verification 1995 Siemens Flash-EEPROM concurrent device/circuit development 1998 STARC 100-nm MOSFET collaboration start Release Activity 2001 Oct. release to vendors HiSIM1.0.0 source code and manual 2002 Jan. release to public June HiSIM1.1.0 Oct. HiSIM Oct. Test release to STARC clients HiSIM2.0.0 source code and manual 2005 May release to CMC members HiSIM2.0.0 July + Verilog-A code Oct. HiSIM Jan. release to vendors HiSIM Dec. HiSIM March HiSIM2.4.0 MOS-AK Workshop ; 14 September
5 Modeled Phenomena in HiSIM2.4.0 [Phenomena] [Subjects] [Phenomena] [Subjects] Short Channel: Reverse-short Channel: Poly-Depletion: Quantum-Mechanical: Channel-Length Modulation: Narrow-Channel: impurity pile-up pocket implant Temperature Dependency: thermal voltage bandgap n i phonon scattering maximum velocity Mobility Models: universal high Field Shallow-Trench Isolation: threshold voltage mobility leakage current Capacitances: intrinsic overlap lateral-field induced fringing Non-Quasi-Static: transient time-domain AC frequency-domain Noise: 1/f thermal induced gate cross-correlation Leakage Currents: substrate current gate current GIDL current Source/Drain Resistances: Junction Diode: currents capacitances Binning Option DFM Option MOS-AK Workshop ; 14 September
6 HiSIM Availability in Commercial EDA Software Type of EDA Software Model Parameter Extraction Circuit Simulation HiSIM2.3.1 Accelicon-MBP, BSIM ProPlus, EXPARA, ICCAP (Nov 07), UTMOST4 ADS, Eldo, FineSime, Hspice, HSIM, Nexxim, SmartSpice, Spectre, Ultrasim HiSIM2.4.0 EXPARA, UTMOST4 Eldo, FineSim, Hspice, HSIM, Nexxim, SmartSpice, Spectre (Dec 07), Ultrasim (Dec 07) HiSIM versions 231 and 240 are available in many commercial EDA tools for circuit analysis. MOS-AK Workshop ; 14 September
7 Outline Overview of Compact-Modeling Approaches Accuracy Aspects of HiSIM2.3.1 and Model Consistency Aspects - Surface-Potential Accuracy - Derivatives - Predictability, Variation Estimate - Inter-Modulation, Noise Speed Versus Accuracy Trade-Off and Position of Leading Compact Models Conclusion MOS-AK Workshop ; 14 September
8 Consistency Property of Surface-Potential Model Q(φ) = ν = µ E: velocity : mobility The surface potential consistently determines charges, capacitances and currents under all operating conditions. MOS-AK Workshop ; 14 September
9 HiSIM Surface Potential at Source and Drain The absolute values of the HiSIM surface potential compare well with 2D simulation. MOS-AK Workshop ; 14 September
10 Bias Dependence & Derivatives of Surface Potential HiSIM accurately reproduces even the bias dependence of the surface-potential derivatives. MOS-AK Workshop ; 14 September
11 Model Extraction for Advanced 45nm Technology W g /L g =2µm/200nm W g /L g =2µm/40nm Measurement HiSIM HiSIM can model even advanced 45nm technology very accurately without the necessity of binning. MOS-AK Workshop ; 14 September
12 Current Derivatives for Advanced 45nm Technology Measurement HiSIM W g /L g = 2µm/40nm The current derivatives of a 45nm technology can likewise be well reproduced with HiSIM. MOS-AK Workshop ; 14 September
13 Gummel-Symmetry Properties HiSIM preserves Gummel symmetry under drain and source exchange up to 3 rd derivatives. MOS-AK Workshop ; 14 September
14 Typical Extraction Result for 90nm CMOS (NMOS) Source: Fujitsu (HiSIM231) Small-error fitting is normally achieved without binning MOS-AK Workshop ; 14 September
15 Typical Extraction Result for 90nm CMOS (PMOS) Source: Fujitsu (HiSIM231) PMOS,NMOS fitting approximately with equal quality MOS-AK Workshop ; 14 September
16 Predictability Test: Nominal Extraction Source: Fujitsu (HiSIM231) MOS-AK Workshop ; 14 September
17 Predictability Test: Changed Channel Dose Source: Fujitsu (HiSIM231) MOS-AK Workshop ; 14 September
18 Predictability Test: Adjustment of Substrate Doping Source: Fujitsu (HiSIM231) Substrate-doping parameter correlates well with physical substrate doping value MOS-AK Workshop ; 14 September
19 Variation Prediction I on variation V th variation (without pocket) Data: HiSIM231 Combined I on, V th variation plot Correct correlation between device and process parameters is required. Surface-potential models like HiSIM are needed. MOS-AK Workshop ; 14 September
20 Inter-Wafer Variation Prediction Long Channel Short Channel Data: HiSIM231 Prediction of inter-wafer variation for Ion, Vth possible MOS-AK Workshop ; 14 September
21 Inter-Wafer Variation Prediction: g m Long Channel Short Channel Data: HiSIM231 Variation predictability is good even for derivatives MOS-AK Workshop ; 14 September
22 Inter-Wafer Variation Prediction: g ds Long Channel Short Channel Data: HiSIM231 Variation predictability is good even for derivatives MOS-AK Workshop ; 14 September
23 Evaluation of Derivative Characteristics Source: Sony (HiSIM231) MOS-AK Workshop ; 14 September
24 Derivatives at Elevated Bias Source: Sony (HiSIM231) HiSIM2.3.1 is in excellent agreement with measurement MOS-AK Workshop ; 14 September
25 Derivatives for Source-Drain Interchange at 0V Source: Sony (HiSIM231) HiSIM2.3.1 is in excellent agreement with measurement MOS-AK Workshop ; 14 September
26 Evaluation of IM3 Characteristics (250nm CMOS) Source: Sony (HiSIM231) MOS-AK Workshop ; 14 September
27 IM3 Simulation in Comparison to Measurement Source: Sony (HiSIM231) Accurate reproduction of IM3 measurements with HiSIM MOS-AK Workshop ; 14 September
28 Evaluation of IM3 Characteristics (90nm CMOS) Model:BSIM4, HiSIM2.3.1, PSP102 Device:90nm technology, NMOS transistor, W/L = 8um / 4um Simulation condition Input:3.5/4.5MHz 2-tone, Output:Po1 3.5/4.5MHz, IM3: 2.5/5.5MHz Simulation: PSS analysis of Spectre-RF Pin -10~0dBm 3.5/4.5MHz - + Pout Output Power Po1:3.5/4.5MHz IM3:2.5/5.5MHz 3.5M 4.5M 2.5M 5.5M IM3- IM3+ Source: Toshiba MOS-AK Workshop ; 14 September
29 IM3 Results for BSIM4, PSP102 and HiSIM2.3.1 Pout(dBm) PSP HiSIM BSIM4 Theory hisim 3.5M psp 3.5M bsim4 3.5M Pin(dBm) Slope=1 IM3(dBm) PSP -70 hisim 2.5M psp 2.5M -75 Slope=3 bsim4 2.5M Theory BSIM4 Pin(dBm) HiSIM Slope in IM3 Analysis (90nm CMOS) BSIM4 : 2.0 (in large disagreement with theory) PSP102 : 2.7 (in improved agreement with the theory) HiSIM2.3 : 3 (in perfect agreement with the theory) Source: Toshiba MOS-AK Workshop ; 14 September
30 1/f-Noise Evaluation Source: Toshiba MOS-AK Workshop ; 14 September
31 Simulation Results Compared with Measurements Source: Toshiba (HiSIM2.3.1) HiSIM2.3.1 accurately reproduces 1/f measurements MOS-AK Workshop ; 14 September
32 Outline Overview of Compact-Modeling Approaches Accuracy Aspects of HiSIM2.3.1 and Speed Versus Accuracy Trade-Off and Position of Leading Compact Models Conclusion MOS-AK Workshop ; 14 September
33 Speed versus Accuracy Trade-Off faster Computational Speed Vth-Based Models Desired Compact Model!? Surface -Potential Models Model Accuracy higher Is it possible to combine high speed and high accuracy to obtain an ideal MOSFET model? MOS-AK Workshop ; 14 September
34 High Cost Functions in the Source Code Static Count of High Cost Functions (Complete Source Code) Dynamic Count of High Cost Functions (average of 9 different bias conditions) Data Source: Silvaco, Oct The number of high-cost functions in the HiSIM2 source code is not larger than for advanced Vth-based models. MOS-AK Workshop ; 14 September
35 Breakdown of HiSIM s Model Evaluation Time Arbitrary Units total CPU extrinsic device characteristics intrinsic device characteristics φ SL iteration φ S0 iteration V gs Data: HiSIM2.4.0 Iteration for surface-potential determination requires only a small fraction of the total model evaluation time. MOS-AK Workshop ; 14 September
36 Model Evaluation Time Comparison L=W=1µm V ds =1V, V bs =0 Evaluation Time HiSIM2.3.1 BSIM4.5.0 HiSIM2.4.0 Model evaluation time of HiSIM2.4.0 is 20% improved and shorter than BSIM V gs MOS-AK Workshop ; 14 September
37 Runtime Comparison of Compact Models Simulated Circuit Types: (90nm CMOS, productively used circuits) ADC, Active Driver, PLL, I/O Module, VCO, DLL, Parity Checker, MUX Buffer Simulator: SmartSpice 64bit, Version 3.3.0B Data Source: Simucad, Dec HiSIM2 executes faster than non-iterative surfacepotential models as well as the latest Vth-based models. MOS-AK Workshop ; 14 September
38 Runtime of Inverter Chains with Different Length.1 Source: NEC Propagation delay times are equalized for all models. MOS-AK Workshop ; 14 September
39 Runtime Comparison in 3 Different Simulators Inverter chains with up to 2024 transistors Source: NEC HiSIM2.3.1 computational runtimes are comparable to BSIM4. The relative runtimes of PSP102.1 consistently increase as a function of the transistor number. MOS-AK Workshop ; 14 September
40 Computational Performance for Large Circuits Source: Simucad HiSIM2.4.0 is faster than BSIM4.5.0 and has comparable memory consumption. PSP runtimes increase strongly above 50K transistors. MOS-AK Workshop ; 14 September
41 Large RF Circuit Simulation Performance Ran on Opteron with 8 2.8GHz CPU and RH.4 OS FineSim Spice v GHz PLL Pre-Layout MOSFET 3k Resistor 0.05k Capacitor 0.7k Vsource k Fvco=M/N X Fref=GHz Tran: 100us, TYP 1.0v, 25C GHz PLL Post-Layout MOSFET - 4k Resistor - 150k Capacitor 60k Vsource k Fvco=M/N X Fref=GHz Tran: 100us, TYP 1.0v, 25C MOS Model Relative Runtime Pre-Layout BSIM HiSIM MOS Model Relative Runtime Post-Layout BSIM HiSIM Source: Magma MOS-AK Workshop ; 14 September
42 Conclusion HiSIM2.3.1 and are a highly accurate MOSFET model based on the full iterative surface-potential concept. HiSIM2.3.1 and have no runtime disadvantage in comparison to surface-potential models using a non-iterative approximation, but rather an advantage. HiSIM2.3.1 and have even shorter computer runtime than the most advanced Vthbased models. HiSIM2 (Versions 231 and 240) is a compact MOSFET model concept with optimized accuracy/speed trade-off MOS-AK Workshop ; 14 September
Contents. Contents... v. Preface... xiii. Chapter 1 Introduction...1. Chapter 2 Significant Physical Effects In Modern MOSFETs...
Contents Contents... v Preface... xiii Chapter 1 Introduction...1 1.1 Compact MOSFET Modeling for Circuit Simulation...1 1.2 The Trends of Compact MOSFET Modeling...5 1.2.1 Modeling new physical effects...5
PSP model update. Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen (NXP Semiconductors) Ramses van der Toorn (Delft University of Technology)
PSP model update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen (NXP Semiconductors) Ramses van der Toorn (Delft University of Technology) MOS-AK, San Francisco 12 December 2012 outline some history
Design cycle for MEMS
Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor
ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model
Invited paper Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model Hans Jürgen Mattausch, Akihiro Yumisaki, Norio Sadachika, Akihiro Kaya, Koh Johguchi, Tetsushi Koide, and Mitiko
UOTFT: Universal Organic TFT Model for Circuit Design
UOTFT: Universal Organic TFT Model for Circuit Design S. Mijalković, D. Green, A. Nejim Silvaco Europe, St Ives, Cambridgeshire, UK A. Rankov, E. Smith, T. Kugler, C. Newsome, J. Halls Cambridge Display
a leap ahead in analog
Analog modeling requirements for HV CMOS technology Ehrenfried Seebacher 2011-12-15 a leap ahead in analog Presentation Overview Design perspective on High Performance Analog HV CMOS Analog modeling requirements
EE5320: Analog IC Design
EE5320: Analog IC Design Handout 3: MOSFETs Saurabh Saxena & Qadeer Khan Indian Institute of Technology Madras Copyright 2018 by EE6:Integrated Circuits & Systems roup @ IIT Madras Overview Transistors
Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor
Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
Topic 2. Basic MOS theory & SPICE simulation
Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/
Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor
Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
NAME: Last First Signature
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 130: IC Devices Spring 2003 FINAL EXAMINATION NAME: Last First Signature STUDENT
problem grade total
Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Name: Recitation: November 16, 2005 Quiz #2 problem grade 1 2 3 4 total General guidelines (please read carefully before starting):
UNIT 3: FIELD EFFECT TRANSISTORS
FIELD EFFECT TRANSISTOR: UNIT 3: FIELD EFFECT TRANSISTORS The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There are
1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY MOSFET Modeling for RF IC Design
1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 MOSFET Modeling for RF IC Design Yuhua Cheng, Senior Member, IEEE, M. Jamal Deen, Fellow, IEEE, and Chih-Hung Chen, Member, IEEE Invited
MOSFET short channel effects
MOSFET short channel effects overview Five different short channel effects can be distinguished: velocity saturation drain induced barrier lowering (DIBL) impact ionization surface scattering hot electrons
FUNDAMENTALS OF MODERN VLSI DEVICES
19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution
Lecture-45. MOS Field-Effect-Transistors Threshold voltage
Lecture-45 MOS Field-Effect-Transistors 7.4. Threshold voltage In this section we summarize the calculation of the threshold voltage and discuss the dependence of the threshold voltage on the bias applied
PHYSICS OF SEMICONDUCTOR DEVICES
PHYSICS OF SEMICONDUCTOR DEVICES PHYSICS OF SEMICONDUCTOR DEVICES by J. P. Colinge Department of Electrical and Computer Engineering University of California, Davis C. A. Colinge Department of Electrical
EE301 Electronics I , Fall
EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials
ECE 340 Lecture 40 : MOSFET I
ECE 340 Lecture 40 : MOSFET I Class Outline: MOS Capacitance-Voltage Analysis MOSFET - Output Characteristics MOSFET - Transfer Characteristics Things you should know when you leave Key Questions How do
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Broadband Communication
INTRODUCTION: Basic operating principle of a MOSFET:
INTRODUCTION: Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying
Session 10: Solid State Physics MOSFET
Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)
Basic Fabrication Steps
Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor
Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and
Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body
ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:
ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline: Metal-Semiconductor Junctions MOSFET Basic Operation MOS Capacitor Things you should know when you leave Key Questions What is the
6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers
6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain- Bandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright 2005
EFFECT OF THRESHOLD VOLTAGE AND CHANNEL LENGTH ON DRAIN CURRENT OF SILICON N-MOSFET
EFFECT OF THRESHOLD VOLTAGE AND CHANNEL LENGTH ON DRAIN CURRENT OF SILICON N-MOSFET A.S.M. Bakibillah Nazibur Rahman Dept. of Electrical & Electronic Engineering, American International University Bangladesh
EE241 - Spring 2013 Advanced Digital Integrated Circuits. Projects. Groups of 3 Proposals in two weeks (2/20) Topics: Lecture 5: Transistor Models
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 5: Transistor Models Projects Groups of 3 Proposals in two weeks (2/20) Topics: Soft errors in datapaths Soft errors in memory Integration
Semiconductor Physics and Devices
Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because
8. Characteristics of Field Effect Transistor (MOSFET)
1 8. Characteristics of Field Effect Transistor (MOSFET) 8.1. Objectives The purpose of this experiment is to measure input and output characteristics of n-channel and p- channel field effect transistors
Lecture #29. Moore s Law
Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday
6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation
Australian Journal of Basic and Applied Sciences, 2(3): 406-411, 2008 ISSN 1991-8178 Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation 1 2 3 R. Muanghlua, N. Vittayakorn and A.
Introduction to VLSI ASIC Design and Technology
Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics
Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam
Georgia Institute of Technology School of Electrical and Computer Engineering Midterm Exam ECE-3400 Fall 2013 Tue, September 24, 2013 Duration: 80min First name Solutions Last name Solutions ID number
ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture
EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 7-1 Simplest Model of MOSFET (from EE16B) 7-2 CMOS Inverter 7-3 CMOS NAND
Variation-Aware Design for Nanometer Generation LSI
HIRATA Morihisa, SHIMIZU Takashi, YAMADA Kenta Abstract Advancement in the microfabrication of semiconductor chips has made the variations and layout-dependent fluctuations of transistor characteristics
A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 831 A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design Gerhard Knoblinger, Member, IEEE,
Total reduction of leakage power through combined effect of Sleep stack and variable body biasing technique
Total reduction of leakage power through combined effect of Sleep and variable body biasing technique Anjana R 1, Ajay kumar somkuwar 2 Abstract Leakage power consumption has become a major concern for
! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture
How is a CMC Standard Model Implemented And Verified in a Simulator?
How is a CMC Standard Model Implemented And Verified in a Simulator? MOS-AK Workshop, Jushan Xie Vice Chairman of the CMC Senior Architect, Cadence Design Systems, Inc. 1 Content Benefit of CMC standard
GaN HEMT SPICE Model Standard for Power & RF. Samuel Mertens MOS-AK Workshop Washington, DC December 9, 2015
GaN HEMT SPICE Model Standard for Power & RF Samuel Mertens MOS-AK Workshop Washington, DC December 9, 2015 Compact Model Coalition @SI2 Standardizing Compact Models Since 1996 Started with BSIM3 Support
! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
Gennady Gildenblat. Editor. Compact Modeling. Principles, Techniques and Applications. Springer
Gennady Gildenblat Editor Compact Modeling Principles, Techniques and Applications Springer Contents Part I Compact Models of MOS Transistors 1 Surface-Potential-Based Compact Model of Bulk MOSFET 3 Gennady
EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05
EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/5 Experiment #1: Reading: Reverse engineering of integrated circuits Jaeger 9.2: MOS transistor layout and design rules HP4145 basics:
EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02
EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic
Organic Electronics. Information: Information: 0331a/ 0442/
Organic Electronics (Course Number 300442 ) Spring 2006 Organic Field Effect Transistors Instructor: Dr. Dietmar Knipp Information: Information: http://www.faculty.iubremen.de/course/c30 http://www.faculty.iubremen.de/course/c30
Solid State Device Fundamentals
Solid State Device Fundamentals 4.4. Field Effect Transistor (MOSFET) ENS 463 Lecture Course by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 4N101b 1 Field-effect transistor (FET)
COMON De-Briefing. Prof. Benjamin Iñiguez
COMON De-Briefing Prof. Benjamin Iñiguez Department of Electronic, Electrical and Automatic Control Engineering, Universitat Rovira i Virgili (URV) Tarragona, Spain benjamin.iniguez@urv.cat MOS-AK, Munich,
INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010
Low Power CMOS Inverter design at different Technologies Vijay Kumar Sharma 1, Surender Soni 2 1 Department of Electronics & Communication, College of Engineering, Teerthanker Mahaveer University, Moradabad
Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
EKV Modeling Engineering Support
EKV Modeling Engineering Support Developments of the Compact Models No. of Model Parameters 1000 100 10 earlyekv LEVEL1 BSIM3v3 MM11v2 BSIM3v2 HiSIM 2.4.0 BSIM2 HSP28 BSIM3v3 PSP BSIM BSIM3v2 BSIM4 BSIM2
Department of Electrical Engineering IIT Madras
Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or
LSI ON GLASS SUBSTRATES
LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
improving further the mobility, and therefore the channel conductivity. The positive pattern definition proposed by Hirayama [6] was much improved in
![improving further the mobility, and therefore the channel conductivity. The positive pattern definition proposed by Hirayama [6] was much improved in](/thumbs/91/107553446.jpg "improving further the mobility, and therefore the channel conductivity. The positive pattern definition proposed by Hirayama [6] was much improved in")
The two-dimensional systems embedded in modulation-doped heterostructures are a very interesting and actual research field. The FIB implantation technique can be successfully used to fabricate using these
Radio Frequency Electronics
Radio Frequency Electronics Active Components II Harry Nyquist Born in 1889 in Sweden Received B.S. and M.S. from U. North Dakota Received Ph.D. from Yale Worked and Bell Laboratories for all of his career
2. TECHNICAL CONTENT
2. TECHNICAL CONTENT 2.1 Abstract: We propose to design and build novel 50W Silicon Carbide single chip power converters, while at the same time demonstrating the capability to design and fabricate SiC
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
Fabrication, Corner, Layout, Matching, & etc.
Advanced Analog Building Blocks Fabrication, Corner, Layout, Matching, & etc. Wei SHEN (KIP) 1 Fabrication Steps for MOS Wei SHEN, Universität Heidelberg 2 Fabrication Steps for MOS Wei SHEN, Universität
MOS Field Effect Transistors
MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact
Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
Fundamentals of Power Semiconductor Devices
В. Jayant Baliga Fundamentals of Power Semiconductor Devices 4y Spri ringer Contents Preface vii Chapter 1 Introduction 1 1.1 Ideal and Typical Power Switching Waveforms 3 1.2 Ideal and Typical Power Device
DIGITAL VLSI LAB ASSIGNMENT 1
DIGITAL VLSI LAB ASSIGNMENT 1 Problem 1: NMOS and PMOS plots using Cadence. In this exercise, you are required to generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence (Use
MOS TRANSISTOR THEORY
MOS TRANSISTOR THEORY Introduction A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the
MOSFET & IC Basics - GATE Problems (Part - I)
MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]
CONTENTS. 2.2 Schrodinger's Wave Equation 31. PART I Semiconductor Material Properties. 2.3 Applications of Schrodinger's Wave Equation 34
CONTENTS Preface x Prologue Semiconductors and the Integrated Circuit xvii PART I Semiconductor Material Properties CHAPTER 1 The Crystal Structure of Solids 1 1.0 Preview 1 1.1 Semiconductor Materials
Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges
Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges Jung-Suk Goo 1, Richard Q. Williams 2, Glenn O. Workman 3, Qiang Chen 4, Sungjae Lee 2, and Edward J. Nowak 2 1 Technology
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
Three Terminal Devices
Three Terminal Devices - field effect transistor (FET) - bipolar junction transistor (BJT) - foundation on which modern electronics is built - active devices - devices described completely by considering
EE70 - Intro. Electronics
EE70 - Intro. Electronics Course website: ~/classes/ee70/fall05 Today s class agenda (November 28, 2005) review Serial/parallel resonant circuits Diode Field Effect Transistor (FET) f 0 = Qs = Qs = 1 2π
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law
Exam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage?
Exam 2 Name: Score /90 Question 1 Short Takes 1 point each unless noted otherwise. 1. Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance
E3 237 Integrated Circuits for Wireless Communication
E3 237 Integrated Circuits for Wireless Communication Lecture 8: Noise in Components Gaurab Banerjee Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore banerjee@ece.iisc.ernet.in
Solid State Devices- Part- II. Module- IV
Solid State Devices- Part- II Module- IV MOS Capacitor Two terminal MOS device MOS = Metal- Oxide- Semiconductor MOS capacitor - the heart of the MOSFET The MOS capacitor is used to induce charge at the
Design and Performance Analysis of SOI and Conventional MOSFET based CMOS Inverter
I J E E E C International Journal of Electrical, Electronics ISSN No. (Online): 2277-2626 and Computer Engineering 3(2): 138-143(2014) Design and Performance Analysis of SOI and Conventional MOSFET based
CHAPTER 2 LITERATURE REVIEW
CHAPTER 2 LITERATURE REVIEW 2.1 Introduction of MOSFET The structure of the MOS field-effect transistor (MOSFET) has two regions of doping opposite that of the substrate, one at each edge of the MOS structure
Lecture 4 -- Tuesday, Sept. 19: Non-uniform injection and/or doping. Diffusion. Continuity/conservation. The five basic equations.
6.012 ELECTRONIC DEVICES AND CIRCUITS Schedule -- Fall 1995 (8/31/95 version) Recitation 1 -- Wednesday, Sept. 6: Review of 6.002 models for BJT. Discussion of models and modeling; motivate need to go
Chapter 2 : Semiconductor Materials & Devices (II) Feb
Chapter 2 : Semiconductor Materials & Devices (II) 1 Reference 1. SemiconductorManufacturing Technology: Michael Quirk and Julian Serda (2001) 3. Microelectronic Circuits (5/e): Sedra & Smith (2004) 4.
55:041 Electronic Circuits
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
A Novel Approach for Velocity Saturation Calculations of 90nm N-channel MOSFET
A Novel Approach for Velocity Saturation Calculations of 90nm N-channel MOSFET Rino Takahashi 1, a, Hitoshi Aoki 2,b, Nobukazu Tsukiji, Masashi Higashino, Shohei Shibuya, Keita Kurihara, Haruo Kobayashi
ECE/CoE 0132: FETs and Gates
ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will
Modeling MOS Transistors. Prof. MacDonald
Modeling MOS Transistors Prof. MacDonald 1 Modeling MOSFETs for simulation l Software is used simulate circuits for validation l Original program SPICE UC Berkeley Simulation Program with Integrated Circuit
UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press
UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth
Lecture 13. Technology Trends and Modeling Pitfalls: Transistors in the real world
Lecture 13 Technology Trends and Modeling Pitfalls: Transistors in the real world Guest lecturer: Jared Zerbe Rambus Inc jared@rambus.com Copyright 2003 by Mark Horowitz 1 Overview CMOS technology trends
Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;
Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known
Microelectronics, BSc course
Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT
Lecture 11 Circuits numériques (I) L'inverseur
Lecture 11 Circuits numériques (I) L'inverseur Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up 6.12 Spring 24 Lecture 11 1 1. Introduction to digital circuits:
LECTURE 4 SPICE MODELING OF MOSFETS
LECTURE 4 SPICE MODELING OF MOSFETS Objectives for Lecture 4* Understanding the element description for MOSFETs Understand the meaning and significance of the various parameters in SPICE model levels 1
SPICE MODELING OF MOSFETS. Objectives for Lecture 4*
LECTURE 4 SPICE MODELING OF MOSFETS Objectives for Lecture 4* Understanding the element description for MOSFETs Understand the meaning and significance of the various parameters in SPICE model levels 1
I E I C since I B is very small
Figure 2: Symbols and nomenclature of a (a) npn and (b) pnp transistor. The BJT consists of three regions, emitter, base, and collector. The emitter and collector are usually of one type of doping, while
MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I
MEASUREMENT AND INSTRUMENTATION STUDY NOTES The MOSFET The MOSFET Metal Oxide FET UNIT-I As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available
Semiconductor Devices
Semiconductor Devices Modelling and Technology Source Electrons Gate Holes Drain Insulator Nandita DasGupta Amitava DasGupta SEMICONDUCTOR DEVICES Modelling and Technology NANDITA DASGUPTA Professor Department
GaN HEMT SPICE Model Standard for Power & RF. Samuel Mertens Si2Con San Jose, CA October 6, 2015
GaN HEMT SPICE Model Standard for Power & RF Samuel Mertens Si2Con San Jose, CA October 6, 2015 Compact Model Coalition @SI2 Standardizing Compact Models Since 1996 Started with BSIM3 Support standardization
Unit III FET and its Applications. 2 Marks Questions and Answers
Unit III FET and its Applications 2 Marks Questions and Answers 1. Why do you call FET as field effect transistor? The name field effect is derived from the fact that the current is controlled by an electric
Analog Technology Forum 2008
Single Vendor Design Flow Solutions for Low Power Electronics Analog Technology Forum 2008 Dr. Ivan Pesic June 25 2008 Simucad 社製品販売サポート Pressure Points on EDA Vendors for Continuous Improvements To be