GaN HEMT SPICE Model Standard for Power & RF. Samuel Mertens MOS-AK Workshop Washington, DC December 9, 2015

Transcription

1 GaN HEMT SPICE Model Standard for Power & RF Samuel Mertens MOS-AK Workshop Washington, DC December 9, 2015

2 Compact Model Standardizing Compact Models Since 1996 Started with BSIM3 Support standardization and making the model usable by industry GaN HEMT first foray into III-V semiconductors Cadence Design Systems, Inc..

3 CMC Progress Chart Plot courtesy of Green Cadence Design Systems, Inc..

4 Historically, III-V semiconductors used to live only live in RF Higher Electron-mobility at high electron density of III-V (including GaN) leads to higher operational frequencies and lower losses Not negligible market-wise GaAs HBT PAs are part of nearly all cell phones The complexity of the chips are smaller Main simulation focus is in frequency domain Cadence Design Systems, Inc..

5 III-V industry has been relatively free of standard models Historic reasons In-house fabrication Small # of transistors Frequency domain Proprietary models Based on public model, but with improvements Considered a competitive edge Limited tools needed Cadence Design Systems, Inc..

6 Advantages of standard model for companies with their own models Augment model staff You don t have to do all the work to develop and maintain models Focus on process specific features Get to physics-based model faster Easier to move to new process Better predictability, scalability and statistical modeling Share the model with partners, customers and vendors Cadence Design Systems, Inc..

7 GaN in Power Electronics since 2009 Reduced power losses for switching applications Low gate charge, and low on-resistance lead to many commercial applications for power conversion (and no QRR) These companies are used to Si integration levels and a Si design flow Standard models are part of that flow Time domain is important No body no inversion, no accumulation can t use Si model Cadence Design Systems, Inc..

8 CMC standardization procedure Four phases 1. Call for models 2. Self-Evaluation 3. Evaluation by CMC members 4. Prepare Standard Cadence Design Systems, Inc..

9 Phase 1 details CMC compiled a list of requirements Technical requirements Support requirements We received 9 applications who returned a checklist and a list of references Committee reviewed the applicants Cadence Design Systems, Inc..

10 Phase 1 requirements - highlights Technical requirements Physical Surface-Potential based (preferred) Gummel-symmetry Support requirements Documentation Support Maintenance Cadence Design Systems, Inc..

11 Phase 1 progress 8 were invited to present at the Q4 13 CMC meeting Anwar (Uconn) Angelov (Chalmers) Antoniadis (MIT) Chan(UST) Khandelwal (UNIK) Martin (LETI) Shur (RPI) Trew (NCSU) 4 candidates found a sponsor to move to next phase Cadence Design Systems, Inc..

12 Phase 2 candidates Angelov (Chalmers) Semi-empirical, semi-threshold voltage based Current standard in RF Antoniadis/Radhakrishna - MVSG (MIT) Charge-based current calculation Khandelwal ASM-HEMT (UNIK) Surface Potential based Martin HSP (LETI) Surface Potential based Cadence Design Systems, Inc..

13 Phase 2 details Two sets of measurement data were supplied Qorvo (RF) Toshiba (Power switching) The 4 candidates were asked to fit this data to their model and then show overlays for a list of plots Cadence Design Systems, Inc..

14 Phase 2 ballot results After downselect ballot, 2 candidates are being reviewed by CMC membership in phase 3 Antoniadis/Radhakrishna MVSG (MIT) Khandelwal ASM-HEMT (UNIK) Really strong candidates for both RF and power switching applications Cadence Design Systems, Inc..

15 MVSG Modeling Approach Slide courtesy of U. Radhakrishna Source- Implicit Tx Intrinsic Tx Gate- Field plate Tx Source- Field plate Tx Drain- Implicit Tx The MVSG model : Charge based model for GaN HEMTs Based on the concept of virtual source top-of-barrier transport of carriers in field effect devices Technology independent model with few physical parameters Models both HV-long channel and HF- short channel GaN HEMTs Cadence Design Systems, Inc..

16 MVSG Terminal Currents Slide courtesy of U. Radhakrishna MVS model extended for long channel employing GCA Source and drain end charge Satura%on velocity I D / W = v sat Cadence Design Systems, Inc.. ( Q ) inv, s + Q inv, d 2 F Vsat Func%on for transi%on from nvsat to vsat E C V S R s V G V D Q i (x o ) v xo R d =µe xo 0 x L x o eff

17 Slide courtesy of U. Radhakrishna MVSG - HV Modeling: Terminal Currents Captures terminal currents in forward and reverse mode Satisfies Gummel symmetry Has good high order derivative behavior Thermal model captures transport over wide temperatures RC time constant captures Cadence Design Systems, Inc.. dynamic self-heating

18 Cadence Design Systems, Inc.. Q dx L x Q i L x g S g ' 0 1 = = dx Q L x Q i L x g D g ' 0 = = Using current continuity and GCA ( ) = , 5, 3, 3, 2, 2 2, 2, d inv s inv d inv s inv s inv d inv s inv g D Q Q Q Q Q Q Q WL Q ( ) + = , 5, 3, 3, 2, 2 2, 2, d inv s inv d inv s inv d inv d inv s inv g S Q Q Q Q Q Q Q WL Q MVSG - HV Modeling: Terminal Charges Field plate parameters from CVs Terminal CVs showing effect of FPs Slide courtesy of U. Radhakrishna

19 Slide courtesy of U. Radhakrishna MVSG - HV Modeling: Charge Trapping ON OFF VDS VON T= 25 C T= 40 C T= 100 C f= 10 KHz f= 5 KHz f= 1 KHz VGQ= -15V VGNQ= 0V Breakdown at 320 V Cadence Design Systems, Inc..

20 VDD Gate Drive Half-Bridge VIN Slide courtesy of U. Radhakrishna MVSG - HV Modeling: Circuit Validation Validated against HVbuck/boost board PWM Level Shi\ + Gate Drive OUT Captures switch node (SN) waveforms and the slew rates accurately SR=60V/ns Empirical model SR=33V/ns Cadence Design Systems, Inc..

21 Slide courtesy of U. Radhakrishna MVSG - RF Modeling: S-Parameters Captures terminal currents, charges of scaled RF-devices Device-level small signal S- parameters modeled Cadence Design Systems, Inc..

22 MVSG - RF Modeling: Large-Signal Source-pull contours Pout contours Load-pull contours Pout contours Slide courtesy of U. Radhakrishna MVSG model calibrated against small-signal can match large-signal Source and load-pull contours are accurate Power sweep captured by the model at different classes Power sweep validation Cadence Design Systems, Inc..

23 Slide courtesy of U. Radhakrishna MVSG - RF modeling: Circuit Validation IEEE P RF-transceiver Transmitter benchmarking Receiver benchmarking 3-stage ring oscillator Oscillation waveforms and phase noise RF-DC boost converter Boost ratio and ripple V INPUT VG = -3.0 V -2.8 V -2.6 V -2.5 V -2.4 V I INDUCTOR V OUT V DRAIN I OUT Cadence Design Systems, Inc.. (a) (b)

24 Slide courtesy of S. Khandelwal ASM-HEMT Modeling Approach 2-DEG Charge and Surface-potential Model Variation of Fermi-level with bias are divided into regions and analytical solutions developed for each region Regions combined as unified model Cadence Design Systems, Inc..

25 Slide courtesy of S. Khandelwal Physics-Based Drain Current Model Drain-current derived by drift-diffusion transport Real device effects accounted in the model Cadence Design Systems, Inc..

26 Slide courtesy of S. Khandelwal ASM-HEMT Access Region Model Non-linear Access Regions Linear (Ohmic) Saturation Cadence Design Systems, Inc.. Slide 26

27 Slide courtesy of S. Khandelwal Physics-Based Modeling of Capacitances All device terminal charges are derived as function of surface-potentials L ( ) Q = Wqn V, V. dx g s g x 0 L x Q = Wqn V, V. dx ( ) d s g x L 0 L x Q = 1 Wqn ( V, V ). dx s s g x L 0 Charge Conservation D CGD G CDS S CGS Cadence Design Systems, Inc.. Slide 27

28 ASM-HEMT Model Features Slide courtesy of S. Khandelwal Consistent I-V and C-V models Non-linear access regions resistance Self-heating effect 1/f and thermal noise Trapping effects Gate resistance Field plate region model Cadence Design Systems, Inc..

29 ASM-HEMT Model Results Slide courtesy of S. Khandelwal DC I-V Characteristics Accurate sub- and above-v off results Cadence Design Systems, Inc..

30 ASM-HEMT Model Results Slide courtesy of S. Khandelwal DC Gm, Gm` and Gm`` model results Accurate Gm and derivatives Cadence Design Systems, Inc..

31 ASM-HEMT Model Results Slide courtesy of S. Khandelwal Multi-bias S-parameters Modeling Cadence Design Systems, Inc.. Slide 31

32 ASM-HEMT Model Results Slide courtesy of S. Khandelwal Multi-bias large signal power sweep results Accurate multi-bias large-signal results Cadence Design Systems, Inc..

33 ASM-HEMT Model Quality Slide courtesy of S. Khandelwal Model passes standard model quality tests Gummel Symmetry AC Symmetry δ cg = C C GS GD Cadence Design Systems, Inc.. GS C + C GD Slide 33

34 Phase 3 CMC members received Model code (Verilog A) Documentation Extraction procedure Parameters sets Testing model Ballot (Q2 16) Cadence Design Systems, Inc..

35 Phase 3 testing Extraction on their own devices Circuit simulation Larger circuits Convergence Performance Time and Frequency domain Noise testing Usability Cadence Design Systems, Inc..

36 Phase 4 Model is made ready for standardization QA suite OP parameters Clean up Clear final code Could take 1-2 quarters Targeting standard model at end of Cadence Design Systems, Inc..

37 CMC Join CMC to help us define this standard Cadence Design Systems, Inc..

38 Acknowledgements Rob Jones (Raytheon) All model candidates for their hard work Ujwal Radhakrishna (MIT) and Sourabh Khandelwal (UCB) for their model summaries CMC members Qorvo and Toshiba for the HW data James Fiorenza (ADI), Vijay Krishnamurthy (TI) and Keith Green (TI) Cadence Design Systems, Inc..

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