Electronic Design Automation at Transistor Level by Ricardo Reis. Preamble

Transcription

1 1 Electronic Design Automation at Transistor Level by Ricardo Reis Preamble

2 1 Quintillion of Transistors

3

4 NM

5 Electronic Design Automation at Transistor Level Ricardo Reis Universidade Federal do Rio Grande do Sul Instituto de Informática - Porto Alegre - RS - Brasil reis@inf.ufrgs.br

6 UTLINE 1. Introduction 2. History 3. Standard Cell 4. CMOS Complex Gates 5. Layout Synthesis 6. Layout Strategies 7. Experimental Results 8. Conclusions

7 History Logic Design Evolution Years 70 : microprocessors hand made computer used just as graphical input End Years 70: Random Logic Z8000 ROMs, PLAs M68000 Years 90: ROMs, PLAs Standard Cell 486, Pentium

8 History Design Automation ESL - Electronics System Level Design Automation UML System C RTL (VHDL, Verilog) Logic Netlist Place & Route (Standard Cells)

9 ntroduction Nowadays Physical Design using Standard Cell is a common practice Should we look for another approach? Why?

10 Standard Cell Approach s it a layout automated approach? NO!

11 Standard Cell Approach Cell characterization Cell performance predictability

12 But nowadays cell predictability is not anymore sufficient to have circuit predictability Connections becomes the central problem!

13 Standard Cell Approach Logic Options Limited to Cells Available in the Library No optimal logic minimization Cells oversized Area

14 Standard Cell Approach Far from Minimization on: - Area - Number of Transistors - Wirelenght - Delay - Power

15 Change of Paradigm

16 Cell Generation on-the-fly

17 History Logic Design Evolution Years 70 : microprocessors hand made computer used just as graphical input End Years 70: Random Logic Z8000 ROMs, PLAs M68000 Years 90: ROMs, PLAs Standard Cell 486, Pentium Next Step: Standard Cell Random Logic Automatic Layout of Cells-on-the-fly

18 Full Custom GND VCC GND Zilog Z8000 detail of the control part using random logic VCC

19 Full Custom VCC Strip Structure GND Detail of the control part of TMS7000 implemented with random logic

20 Standard Cell Approach X Cell On-the-fly Approach Transistor Level Design Automation

21 challenge To develop a CAD system for the automatic physical design of integrated circuits tuned for the requirements of submicron technologies: smaller area smaller delay (wirelenght reduction) (wirelenght reduction) less power consumption

22 Connections becomes the central problem! Challenge: how to reduce wirelength?

23 Challenge: how to reduce wirelength? - area reduction - use of complex gates (SCCG) - improvement of routing and placement algorithms

24 Using Static CMOS Complex Gates (SCCG) with cell generation on-the-fly It is possible do to an extreme logic minimization Freedom to Logic Designers!!!!

25 Example A B C D S S = A + ( B + (C+D)) A B S C D 14 Transistors

26 Use of SCCG S = A + ( B + (C+D)) S = A + ( B.(C+D)) B D C A A S B C S A D D B C 8 Transistors

27 Use of SCCG S = A + ( B + (C+D)) S = A + ( B.(C+D)) A A B C D S B C D S 14 Transistors 8 Transistors

28 Automatic Layout Synthesis Using Complex Gates (SCCG) NUMBER OF SERIAL NMOS TRANSISTORS NUMBER OF SERIAL PMOS TRANSISTORS

29 ower eduction I leakage is become important in submicron circuits. It is function of the number of transistors

30 Routing the solutions produced by academic and industrial tools are in average within 1.43 to 2.38 times the optimal solutions considering wirelength C-C. Chang, J. Cong, M. Xie. Optimality and Scalability of Existing Placement Algorithms. ASPDAC 2003

31 FOTC Routing FOTC approach (Full-Over-The-Cell Routing) All conections are over the active zones

32 ayout trategies

33 Layout Strategies - transistor topologies - management of routing in all layers - VCC and Ground distribution - clock distribution - contacts and vias management - body ties management - transistor sizing and folding

34 Layout Strategies Transistor topologies - horizontal - vertical - doglegs (different directions) - folding

35 Transistor Folding 35

36 Transistor Folding 36

37 Layout Strategies Routing Management - priority tracks schema - routing layers priority - routing layers directions

38 Layout Strategies VCC and Ground Distribution - borders of the strip - middle of strips (between P and N diffusions) - over the transistors Layer (metal 1, metal 2,...)

39 Power Lines over the transistors TROPIC3

40 Power Lines between P and N plans Optimized Jog in polysilicon wire Aligned pins with jog in polysilicon. Transistor not aligned Not aligned pin P diffusion Connetion between N and P plan in metal1 vcc (metal2) gnd (metal2) N diffusion Over-the-cell routing Metal1 to connect supply line TROPIC3

41 Power Lines at the Strip Borders Parrot1

42 Layout Strategies - contacts and vias management - body ties management

43 Layout Strategies contacts and vias management (towers of vias)

44 Compaction Results Summary: 8150 Variables Constraints runtime: 20 segs Weights: Diffusion 3 Poly 3 Metal 1 Transistor-Level Automatic Layout Generation of Radiation-Hardened Circuits

45 Compaction Results Poly lines Reduction Transistor-Level Automatic Layout Generation of Radiation-Hardened Circuits

46 Compaction Results Metal lines Reduction Transistor-Level Automatic Layout Generation of Radiation-Hardened Circuits

47 Compaction Results Diffusion Reduction Transistor-Level Automatic Layout Generation of Radiation-Hardened Circuits

48 Physical Design Flow

49 Logic Netlist Partitioning and Placement Routing Cell Generation Automatic Characterization Timing Power Circuit Layout

50 Layout Generation Flow Circuit Placement Specifications Design Rules Transistor Placement Layout Generation Routing Layout 50

51 Wirelength Placement with wirelength reduction

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53 Congestion Congestion is an important problem because it can forbid a complete routing Routability

54 Compromise: Routability and Wirelength Reduction

55 Parrot Layout Style

56 Layout Generated Automatically with Parrot Tool Suite

57 432 TROPIC PARROT 804 transistors Delay: % Area: %

58 499 TROPIC PARROT 1556 transistors Delay: % Area: %

59 880 TROPIC PARROT 1802 transistors Delay: % Area: %

60 1355 TROPIC PARROT 2308 transistors Delay: % Area: %

61 Results: Layouts

62 Results: Layouts --- ( transistors JK1 (34 62

63 ADD32

64 Adder Adder Mux Register

65 Results: Layouts Non-Complementary Logic ( transistors LBBDD_ F177F7FFF (68 Runtime: 36 min L.S.da Rosa Jr., F.Marques, T.M.G.Cardoso, R.P.Ribas, S.S.Sapatnekar, A.I.Reis, Fast Transistor Networks from BDDs. SBCCI 2006, pp

66 Data Path Design Automation

67 Multiplier Carry-Save 4x4 Standard Cell (Cadence Flow) Generated with our Data Path Compiler

68 Multiplier Carry-Save 4x4 Standard Cell Cell Compiler Gain (%) Number of Cells Number of Transistors Area (µm 2 ) Delay (ps) Power (mw)

69 Conclusions

70 Conclusions Cell generated on-the-fly target to their environment Area reduction Reduction on the number of transistors Cell library free Wirelength minimization Power Reduction Delay Reduction

71 Conclusions Let s do Transistor Level Design Automation

72 Electronic Design Automation at Transistor Level Ricardo Reis Universidade Federal do Rio Grande do Sul Instituto de Informática - Porto Alegre - RS - Brasil reis@inf.ufrgs.br