Holistic View of Lithography for Double Patterning. Skip Miller ASML

Transcription

1 Holistic View of Lithography for Double Patterning Skip Miller ASML

2 Outline Lithography Requirements ASML Holistic Lithography Solutions Conclusions Slide 2

3 Shrink Continues Lithography keeps adding value Average of multiple customers input 200 Logic / SRAM Resolution/half pitch, "Shrink" [nm] DRAM k ~ 0.35 NAND Flash k ~ 0.30 Logic NAND 6 Transistor SRAM Cell k ~ 0.44 DRAM 1/1/15 1/1/14 1/1/13 1/1/12 1/1/11 1/1/10 1/1/09 1/1/08 1/1/07 1/1/06 1/1/05 1/1/04 1/1/03 1/1/02 Year of production start* * Note: Process development 1.5 ~ 2 years in advance Slide 3

4 Most Likely Lithography Roadmap DPT will bridge gap between single exposure 193nm & EUV Half pitch (nm) Year λ (nm) NA Double Patterning Low k 1 challenge Infrastructure challenge k1 = (half-pitch) * numerical aperture / wavelength Most likely Opportunity Unlikely Slide 4

5 Options to print below immersion single exposure limit Cost, complexity and cycle time *Wafer does not leave the exposure system between the two exposures Single exposure *Wafer preferably does not leave the litho cell between the exposures Double exposure *Wafer leaves litho cell for etch between the exposures Litho DPT - LFLE Litho DPT - LELE Spacer DPT SiON /HM Etch Clean Strip Film Etch Metrology Develop Expose Top coat Resist BARC SiON / SiC Hard Mask Device film Si Slide 5

6 Required Litho CD Uniformity vs Half Pitch DPT drives need for significant improvement in CDU % CD Single Expose 193 nm SE-CDU Spacer-CDU Litho DPT-CDU CD Uniformity [nm] % CD Litho DPT 3% CD Spacer DPT Metrology precision: 20% of CDU 7% CD Single Expose EUV Half Pitch [nm] Slide 6

7 Required Litho Overlay vs Half Pitch DPT drives need for significant improvement in Overlay % of CD Single Expose/ spacer DPT 193 nm SE-Overlay DPT-Overlay 10 Overlay [nm] % of CD Litho DPT 193 nm 20% CD Single Expose EUV 2 Metrology precision: 0 10% of Overlay Half Pitch [nm] 10 Slide 7

8 Lithography Requirements Summary DPT requires improved overlay & imaging, as well as higher productivity Litho exposure equipment parameter as percentage of CD Single exposure Litho double patterning Spacer double patterning CD 7% 3.5% 3% Overlay (depending on DFM) 20% 7% 7-20%* #mask steps # process steps relative to single exposure Requires improved productivity for CoO Requires improved imaging & overlay control * Depending on the amount of Design For Manufacturing effort Slide 8

9 Outline Lithography Requirements ASML Holistic Lithography Solutions Conclusions Slide 9

10 DPT Requires Holistic Litho Optimization Combination of Computational and Wafer lithography Mask definition New NXT Platform for Lithography Metrology Illumination setting Mask making Scanner settings Printed wafers Device pattern Computational Litho Scanner-to-pattern tuning Wafer Litho Measuring CD & Overlay Slide 10

11 NXT:1950i Innovations for Superior Overlay & Imaging at 200wph Reticle Stage with Improved Dynamics NXT is extendable with field upgrades Improved lens performance & control Planar wafer stages Grid plate position measurement (encoder) Slide 11

12 NXT wafer stage metrology impact on overlay Y- coordinate X-coordinate Current stage metrology Interferometer 300 mm stage Overlay [nm, 99.7%] Overlay: < 4 nm System [#] (ArF 0.93NA) Improved metrology Grid plate <15 mm stage Overlay [nm, 99.7%] Overlay: < 2 nm Wafer [#] (prototype) Slide 12

13 NXT: improved overlay at high throughput zone alignment (30 mm) radius 6 parameters model Throughput [%] NXT:1950i + Grid-Align NXT:1950i scheme robust for grid deformations % 8 minimum for zone alignment typical usage minimum for 6 parameters 6 REDUCE NOISE statistical averaging of process effects expected usage 4 2 On Product Overlay M+3S [nm] Number of alignment mark pairs Number of alignment mark pairs MEASURED OVERLAY THROUGHPUT Slide 13

14 NXT innovations bring immersion overlay < 2 nm x, y : 1.6, 1.7nm 3 day overlay 8 X Y 6 4 Lot x,y (nm): 2.0,1.8 5 nm 99.7% x: 1.6 nm y: 1.7 nm day overlay X Y Lot x,y (nm): 1.7, Slide 14

15 Ultimate half pitch at 1.35NA: 36.5 nm Large process window with 10% EL and 500nm DOF F=-0.12um F=0.0um F=0.12um F=-0.21um 15 k 1 =0.255! F=0.21um F=-0.3um NA=1.35 σ=0.989/0.913 Dipole-20 degree X Y polarization 6% att. PSM exposure latitude [%] % EL 500 nm DOF DOF [um] Slide 15 F=0.3um

16 CD uniformity (3σ) below 0.9 nm with extreme dipole 38-nm dense lines measured CD uniformity Full wafer CDU = 0.87 nm without reticle and process correction frequency Settings: 1.35 NA with dipole 20 o and sigma inner 0.90, sigma outer CD [nm] Slide 16

17 Through lot wafer to wafer variation CDU <0.3 nm 38-nm dense lines with dipole illumination 3sigma (nm) full wafer CDU intra-field CDU CD CD (nm) 0.0 NA=1.35 Sigma=0.98/0.90 DipoleX-20 TE-polarized Pooled Wafer No correction applied for processing-profiles Slide 17

18 ASML system throughput roadmap drives CoO ATP throughput [WPH] mm stepper Wavelength Wafer size Immersion ArF KrF i-line g-line 200 mm stepper 150 mm 200 mm 300 mm 200 mm scanner 300 mm NXT 300 mm AT & XT Year of introduction Source: ASML Slide 18

19 NXT Immersion design : single digit defect level 45nm Pattern Defect Test (10 wafers) 20 Printing Particles Immersion specific 15 #defects KLA2800 metrology Using top-coat TCX041 (SRCA 68 degree) mean Wafer number Slide 19

20 20 15 NXT Immersion design : single digit defects across multiple systems 45nm Pattern Defect Test (10 wafers) on 4 systems Printing Particles Immersion specific #defects KLA2800 metrology Using top-coat TCX041 (SRCA 68 degree) Average System Slide 20

21 Holistic litho enables low k 1 / DPT applications Scanner tuning knobs DoseMapper for optimum CD Uniformity Correction Application specific recipe Scanner specific performance Mask Enhanced Computational Lithography Mask OPC/RET Optimization GridMapper for minimizing Overlay grid residuals ImageTuner for Application specific lens setup Free form DOE/Flexible illuminator for Application specific illumination optimization Improved Productivity, Overlay and Critical Dimension Uniformity (CDU) Faster ramp up and improved yield Metrology control loops Baseliner for Twinscan stability, matching and set-up + = Source -mask optimization Freeform illuminator/mask Pattern Matcher for consistency across installed base Slide 21

22 Co-optimization of source shape and pattern split Enables optimum process window Source Mask Overlapping PW 10% EL CD Uniformity Source Mask 100 nm The illumination Source & Mask are co-optimized to improve process window and CD Uniformity 150 nm By combining source expertise from ASML and mask expertise from Brion, enables larger process window with better CD Uniformity Slide 22

23 Litho and application aware double patterning Example: 2D logic gate aware split & model based overlay stitching Standard Gate aware split Poor pattern split on critical gate Optimal pattern split on overlay tolerant locations Diffusion Poly Split 1 Poly Split 2 Slide 23

24 DPT requires a Fast & Flexible Source ASML FlexRay Slide 24

25 Holistic Litho Solution to optimize DPT CDU Pitch =128 nm Calculate Dose & Grid Map to optimize final CDU Etch &2nd litho step Etch CD metrology of lines & spaces Pitch = 64 nm S2 L1 S1 L2 S2 L1 S1 L2 S2 L1 S1 L2 Slide 25

26 Litho patterning process control for CD and Overlay Measurements of final 32 nm L/S using angular resolved scatterometry Raw etched poly CDU Mean CD Overlay between litho 1 and 2 < 4.9 nm < 7.0 nm < 6.3 nm 99.7% OVL X = 4.0 nm 99.7% OVL Y = 4.2 nm 10 nm Line1 Line2 DoseMapper recipe DoseMapper recipe Optimum GridMapper recipe < 2.8 nm < 3.8 nm < 0.8 nm 99.7% OVL X = 3.2 nm 99.7% OVL Y = 3.4 nm DoseMapper corrected etched poly CDU Slide 26 mean CD Data generated in collaboration with IMEC 10 nm

27 Spacer litho control improves wafer CDU Measurements of final 32 nm L/S using angular resolved scatterometry Uncontrolled S 1 3σ=3.92 S 2 3σ=3.46 3σ S 1 -S 2 =6.06 3σ L1,L2=2.12 Controlled S 2 3σ=2.74 S 1 3σ=2.1 3σ S 1 -S 2 =3.27 3σ L1,L2=1.99 Slide 27

28 Outline Lithography Requirements ASML Holisitic Lithography Solutions Conclusions Slide 28

29 ASML Delivers Solutions to Drive Industry Shrink DPT will bridge gap between single exposure 193nm & EUV 200 Resolution, Shrink (nm) AT:850 AT:1200 ASML Product Introduction Logic NAND XT:1400 DRAM XT:1700i XT:1900i Immersion Double Patterning Holistic Litho 30 NXT:1950i EUV EUV 00 Source: ASML Year of Production Start Slide

30 Conclusions DPT will be used as a litho solution to enable future shrink as bridge between single exposure immersion & EUV DPT requires aggressive overlay & imaging requirements at high productivity NXT:1950 delivers required overlay & imaging at high tput to enable a cost effective DPT solution Co-optimization of source and pattern split via Brion products maximizes process window for DPT FlexRay delivers fast & flexible source shapes required for lowk 1 / DPT technology Holistic Litho optimization delivers solutions to optimize cdu & overlay to meet future lithography requirements Slide 30

31 EUV Double Patterning Immersion MC Escher THANK YOU! Slide 31