Beyond Immersion Patterning Enablers for the Next Decade

Transcription

1 Beyond Immersion Patterning Enablers for the Next Decade Colin Brodsky Manager and Senior Technical Staff Member Patterning Process Development IBM Semiconductor Research & Development Center Hopewell Junction, NY Semicon Europa October 2011

2 Lithography: Rayleigh vs. Moore Rayleigh: Minimum half-pitch feature = 2 k 1 l / NA Moore: Density halves every 2 years To keep up with Moore, Rayleigh must decrease k 1, l or increase NA: Numerical Aperture: NA Immersion High Index Immersion Wavelength: l EUV (NA: x?) Complexity of Imaging Solution: k 1 Aggressive Resolution Enhancement & Double Patterning Resolution Enhancement Techniques (RETs) allow driving k 1 toward physical limit (0.25) by aggressive manipulation of optical wavefront Co-optimization with design and computationally solved conditions drive to most cost effective solutions Double / Multi Patterning allows extension of optical below k1 < 0.25, but has cost implications: increased process steps and mask count Unprecedented material and process innovations will be required to close the gap to EUV readiness Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

3 Technology Innovation Pipeline Fundamental Research New materials, processes, & devices Advanced Semiconductor R&D Innovation in process & packaging technology Technology Development Multi-company co-located joint development Si Nanowires Low Dimensional Carbon Electronics Phase Change Memory (PCM) Silicon Nanophotonics IBM Almaden & Yorktown Process Element & Device Exploration (Pre-T0 Alliance) Adv. Packaging Center / 3Di Equipment Dev. Center (EDC) Sematech Albany Nanotech Center High Perf SOI Technology Alliance Foundry Bulk Technology Alliance Packaging Development Alliances IBM East Fishkill IBM Bromont Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

4 Albany Nanotech Research Facility. A unique partnership between New York State, IBM, College of Nanoscale Science & Engineering (CNSE), SEMATECH and leading edge semiconductor manufacturers and suppliers from around the globe on a state of the art pilot line. Developing a world class high technology work force for New York, IBM and the world. No corollary exists in the industry for collaboration between academia, State government and industry Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

5 Collaborative Innovation Ecosystem in Albany Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

6 East Fishkill Technology Development Co-exists with state of the art manufacturing facility spanning many technology nodes Uniquely flexible manufacturing and tooling capabilities Deep library of yield-proven building blocks Diverse and flexible toolsets An ideal environment to test the yield limits of new process elements Power7 Watson Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

7 Cost ($M) Relative % Improvement 180nm 130nm 90nm 65nm 45nm 32nm Why Collaborate? IBM Transistor Performance Improvement Gain by Traditional Scaling Gain by Innovation Industry Realities: 100% Technology advancements have shifted from scaling to innovation Process development costs escalating 80% 60% 40% Benefits of Collaboration: Shared cost of R&D Greater R&D resources Shared learning Synergistic engineering skills Manufacturing sourcing flexibility for leverage & risk mitigation Collaborate on design enablement IP (i.e., design kits, libraries, DFM, & design services) Collaboration brings together system-level, circuit design, process, packaging, & manufacturing skills Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12, % 0% Process Development Cost by Node $1,800 $1,500 $1,200 $900 $600 $300 $0 180nm 130nm 90n m 65nm 45nm 32nm

8 Lithography Solutions: Historical Perspective Lithography Research Tool Prototype Tool First Full Chip Production KrF (248nm) ArF (193nm) Immersion ArF 1997 Nov Nov EUV (13nm) Implementation of new lithography solutions required long term development programs with industry-wide cooperation EUV presents an extraordinary challenge even in this historical context Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

9 Immersion (ArFi) Development Timeline at IBM Industry moves away 157 nm (F 2 ) IBM initiates ASML partnership on ArFi 1150i Prototype in Holland 1150i shipped to ANT; 1 st images in Oct. IBM demos industry 1 st chip with ArFi in Dec. Collaboration on industry standards with ASML & SEMATECH Collaboration on materials solutions with resist vendors & academia 45 nm manufacturing with multiple critical levels of ArFi Enabled P7 ramp i (1.2 NA) in NY Manufacturing Tool 45 nm qualification i for ArFi implementation in dev Bridge Tool 45 nm development Defectivity Learning 2006 Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

10 Challenges of Introducing a New Litho Wavelength Immersion (ArFi) Water in Scanner Materials Interactions Hyper-NA (>1) Same Wavelength Same Masks Same Resists EUV High Vacuum New Wavelength (13.5nm) Reflective Optics New Mask No Pellicle New Resists Immersion presented many challenges, but many elements ported for dry ArF EUV is a significantly more challenging endeavor, requiring more innovative comprehensive solutions Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

11 Power (W) Primary EUV Technology Challenges Source Power & Reliability ADT NXE 3100 NXE 3300 LER Resolution Resist Collapse Sensitivity Image Placement (to Match Fleet) DEFECTIVITY: WAFER MASK SCANNER Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

12 Cost Effective Lithography? For any solution, the cost of scaling must make economic sense Cost per what? Wafer? Chip? Transistor? CoO models are specific to each fab, market segment Different answer for each market segment: memory, consumer, MPU, server Different answer for each product / part number: wafers/mask EUV: Throughput, reliability, yield, mask cost Availability DPL: Throughput, reliability, yield, mask cost For any solution to be economically feasible it must be: Available Free of cost prohibitive processing How many masks per level? Proven robust for manufacturing Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

13 193 nm Lithography Extension: Continuous Innovation nm 32 nm 22 nm 14 nm 10 nm Immersion (ArFi) 2 nd Generation Immersion 3 rd Gen ArFi w/ Source Mask Optimization (SMO) 4 th Gen ArFi w/ SMO & Double Patterning (DPL) EUV (or MPL) 2 Year Cycles to Enable 50% Area Shrink Node-to-Node Advancements in tooling, RETs, materials, controls Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

14 Double Patterning Techniques Many strategies under consideration: Litho-Etch-Litho-Etch (LELE, aka DE 2 Double Exposure, Double Etch) Litho-Litho-Etch (LLE, aka DETO Double Expose Track Only) Sidewall Image Transfer (SIT, aka SADP Self Aligned Double Patterning ) Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

15 Positive Tone vs Negative Tone Dissolution Positive Tone Develop Process Aqueous Developer Expose PEB & Develop Post Develop Structure Negative Tone Develop Process Organic Solvent Developer Organic solvent developer with positive tone like resists, results in a negative tone process Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

16 Double Patterning of Line / Space: Negative vs Positive Tone Development NTD PTD EL max (%) 5% EL (nm) MEEF LER (nm) Process window for trenches printed 36nm at pitch 128nm for NTD LELE The use of bright field mask in combination with NTD process gives wider process window than a standard process using dark field imaging and positive tone TMAH developer. Bright field imaging of contacts, vias, metals: key enabler for extending optical lithography via single or double patterning Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

17 Tone-Inversion Sequence Overcoat Overburden Etch Resist Extraction & Amplification Etch for Trench Control Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

18 Tone Inversion vs Negative Tone LELE: Post Etch M2 Tone Inversion Pitch Split (LLE) Negative Tone Develop Pitch Split (LELE) 18 Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12, /26/

19 3 Metal Build Patterned by Tone Inversion Pitch Split Electrical Test Electrical Yield Opens 97% M3 Shorts 100% Isolated Via 100% M2 M1 19 Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

20 The Defect Challenge Lack of a mature EUV solution will drive ingenuity in extending 193 nm immersion lithography to fill the void Many of these solutions will introduce new materials and processes not yet exercised in manufacturing Negative tone solvent-based developer Freeze develops 193 immersion lithography over severe topography Resist extractions Multi-patterning solutions require exceptional defect learning rates Must achieve composite D0 consistent with D0 roadmap for a single pattern level More than ever before, we need aggressive defect learning early in the technology cycle Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

21 Increasing role for electrical learning vehicles Dedicated yield learning masks and process routes are increasingly common in wafer fabs Defect Detection Method Optical/SEM Electrical Single level and integrated module builds Eliminates optical capture rate concerns Time to detect Hours Days Cost $$-$$$ / wafer $$$-$$$$ / wafer Optical inspections continue to have value Fast, non-destructive testing for controls Vendor access On site, via consortia, IDMs/Foundries IDMs/Foundries Good pre-requisite for screening, but limited capture rate for many failure modes Capability Necessary but not sufficient The final arbiter Electrical learning vehicles remain a relatively untapped opportunity for vendors Important proving ground More data transparency can provide credibility and help align industry momentum around successful candidates Requires a new level of collaboration Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

22 % substrate reflectivity substrate reflectivity (%) Reflections on Trilayer Trilayer enabled 193 nm extension to high-na immersion lithography High NA reflectivity challenges solved with familiar track-based processes Conventional Single-Layer BARC x polarized x&y 3 x polarized polarized x&y polarized 2.5 y polarized y polarized 1% ceiling value 2 1% 1.2 ceiling NA value NA nsinq (NA) Spin-on Trilayer Solution nsinq Now a proven manufacturing solution for multiple technology nodes This did not come for free many process challenges solved Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

23 Reflections on Trilayer Consider a common 32 nm patterning stack: 4 spin-cast layers Twice the defect opportunity as compared to typical 65 nm stack Twice the opportunity for inducing micro-bridging Two layers are not immediately imaged Defects revealed only after a destructive substrate etch/strip process Topcoat Photoresist Spin-on Si Hardmask Planarization and Transfer Layer Substrate Requiring destructive evaluations erodes many advantages of optical inspection Wafer and processing cost increases Time to process increases Electrical learning vehicles become increasingly attractive Do we want any doubts about the results after making these investments? One type of defect but many root causes Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

24 Making Trilayer Successful Photochemical filtration and dispense recognized as a critical element Accelerated defect learning key to maintaining composite D0 roadmap Motivated new partnerships with deeper level of collaboration Access to electrical learning vehicles Access to state of the art optical inspection tools Opportunity to prove process candidates over extended trials in a true manufacturing environment Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

25 Resist filtration improvements Dual-membrane filtration reduces variability and improves yield Data collected on specialized yield learning vehicle Test capability can discriminate single-line bridges versus larger multi-line bridges Optical inspection unable to reveal these differences Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

26 Cumulative Population Transfer Layer Improvements Buried transfer layers increase the detection challenge Signals not visible in post-photo optical monitoring Low capture rate after etch / metallization Often chasing low-level and variable signals Comparing two solvent prewets for a buried transfer layer 100% 80% Solvent 1 Solvent 2 60% Electrical test quickly points towards improved solutions 40% 100 % capture rate with strong signal strength 20% 0% Electrically Extracted D0 Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

27 Electrically extracted D0 Photochemical Solvent Purity PPB levels of metallic contaminants can drive patterning failures Commonly observed as microbridged lines or silicon spikes after pattern transfer Not detected in photo sector with optical defect monitors Must tradeoff cost of purification versus photochemical savings No photochemical prewet Single level of photochemical prewet Two levels of photochemical prewet Data from early 32 nm process highlighted critical defect mode not detectable with conventional monitoring Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

28 What can we expect with negative tone developer? Dramatically increased exposure to similar solvents Aggressive purification specs will drive more photochemical expense A 1 ppb incoming supply spec is estimated to drive $0.25/wafer pass for negative tone develop solvent Solvent prewet experience suggests part-pertrillion specs will be required Total Dispense (ml) Solvent Prewet Solvent Develop Residence tim e on w afer (seconds) Key opportunity for proven fab-level and point of use purification solutions Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,

29 Summary EUV is inevitable but delayed Field remains wide open for creative 193 nm process-oriented extensions Strong collaborative alliances create the necessary climate to achieve proof of concept demonstrations Creativity must be married to disciplined defect learning Deeper collaboration models extending into wafer fabs will be required to meet the challenge Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12,