Leadership Through Innovation Litho for the future

Transcription

1 Leadership Through Innovation Litho for the future Deutsche Bank Access Asia Conference 2010 Singapore Craig De Young VP Investor Relations and Corporate Communications May 12, 2010 Public

2 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements, including statements made about our outlook, realization of backlog, IC unit demand, financial results, average selling price, gross margin and expenses. These forward looking statements are subject to risks and uncertainties including, but not limited to: economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors (the principal product of our customer base), including the impact of general economic conditions on consumer confidence and demand for our customers products, competitive products and pricing, manufacturing efficiencies, new product development and customer acceptance of new products, ability to enforce patents and protect intellectual property rights, the risk of intellectual property litigation, availability of raw materials and critical manufacturing equipment, trade environment, changes in exchange rates and other risks indicated in the risk factors included in ASML s Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. Slide 2 Public

3 Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 3 Public

4 ASML : Leading supplier of lithography equipment to the semiconductor industry Headquarters: Veldhoven, The Netherlands Market Cap approx 10 B Slide 4 Public

5 ASML s growing market share 70% 60% 50% 40% 30% 20% 10% 7,000 6,000 5,000 4,000 3,000 2,000 1,000 WW M$ ASML market share 70% 60% 50% 40% 30% 20% 0% World Wide Market [M USD] ASML Revenue Market Share [%] 10% 0 0% Sources: VLSI, Gartner ( ), SEMI ( ) 2009 ASML 67% Nikon 29% Canon 4% $ Total market: $2500 million Slide 5 Public Source: ASML, SEMI

6 ASML: #2 semiconductor equipment supplier with approx employees worldwide 19% sales 5% 76 % sales ASML employees in US: 1,470 ASML employees in Europe: 3,800 ASML employees in Asia: 1,327 Over 60 sales and service offices located worldwide Source: ASML Q4, 2009 Slide 6 Public

7 Semiconductor food chain 2010 Forecast Source: Gartner Dataquest & VLSIResearch & ASML TSMC Hynix Micron Capex 22 B *On April 14,2010 ASML guided 2010 total revenues > 3.8B. 3.4 billion is an indication of equipment only revenues. Semiconductor sales 204 B Samsung Intel Slide 7 Public Semiconductor sales 280 B IBM Applied Materials KLA- Tencor Toshiba Fab equipment 17 B Tokyo Electron Canon Nikon LAM Research Litho 4.4 B ASML ASML > 3.4B*

8 Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 8 Public

9 Enabling Moore s Law towards 10 nm resolution Lithography supports shrink roadmap 200 Logic Resolution/half pitch, "Shrink" [nm] AT:1200 XT:1400 XT:1700i XT:1900i NXT:1950i DRAM NAND NXE:3100 ARF ARFi 20 NXE:3300 EUV Year of production start* *Average customer input, update Jan 10 Slide 9 Public

10 The drive (Moore) the way (Rayleigh) Moore's Law Rayleigh s Equation Gordon Moore The capacity of each new chip doubles every months Critical Dimension (CD) shrinks 30% each generation Lord Rayleigh CD= k 1 * λ NA reduce wavelength increase NA lower k 1 Slide 10 Public

11 Wavelength down, NA up to meet customer needs Resolution, "Shrink" (nm) nm Technology transitions DRAM (working memory in PC s) Logic (microprocessors, the brains of PC s) 193 nm NAND Flash (special memory, used in, for example mp3 players) 20 EUV 13.5nm Exposure wavelength Year of production start* 15 *Process development 1.5 ~ 2 years in advance. Slide 11 Public

12 Other critical parameters in Lithography Lithography determines dimensions and overlay Imaging How small can you print 1/1,000 mm Lowest cost per chip Overlay How accurate can you print Productivity How fast can you print Slide 12 Public

13 Lithography is the motor of the semiconductor industry In 30 years: Resolution from > 1,200 nm to < 20 nm System prices from <0.5M per system to >60M 13.5nm 193nm 248nm 365nm 436nm 2010 s NXE EUV systems 2000 s 1990 s PAS 5000 Steppers PAS 2000 Steppers Resolution: <500 nm Resolution: >1µm overlay: Slide nm PAS 5500 steppers/scanners Resolution: 400 to 90 nm overlay: 100 to 12 nm overlay: 100 nm Public NXT:Twinscan Resolution: 100 to 38 nm overlay: 20 to 4 nm Resolution: 32 to <20 nm overlay: 2 nm

14 Market share gained by delivering technology in time 12 & ArF ArFi ASML Market Share (revenue) 60% 50% 40% 30% 20% 10% Timely introduction Reliable introduction Cost effective 8 & i-line 6 & early i-line KrF & Step & Scan 0% Time Source: ASML, SEMI Slide 14 Public 2000

15 Agenda ASML Overview Technology Leadership Critical Mass through Scale and an Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 15 Public

16 Cost of Technology Platform PAS stepper 5500 scanner R & D TWINSCAN ArF dry TWINSCAN ArF wet R&D 50 M 125 M 250 M 500 M 1,000 M 1,500 M EUV Required Revenue Average Selling Price Required number of tools 333 M 850 M 1,700 M 3,500 M 6,500 M 10,000 M 1 M 3 M 7 M 16 M 35 M 60 M Number of tools for return on R&D Source: ASML, R&D estimates ASML only Slide 16 Public

17 Commitment to innovation requires a strong player with a certain scale (gained though market share) R& D spend supports continued technology leadership ASML R&D investment (excl. Zeiss for lenses) Total Sales (M ) R&D Investment (M ) Total sales M R&D investment M Source: ASML Slide 17 Public

18 Internal resource spending less than half of total R&D R&D expenses 2009 Expected R&D expenses 2014 Farm out (TNO, TU's, others) Farm out (TNO, TU's, others) Philips, VDL and others ASML companies Brion and Optics Carl Zeiss 9% 4% 9% 18% Various 3% Material 3% 7% Cymer labor 47% Philips, VDL and others ASML companies Brion and Optics Various 3% Material 5% 10% 6% 15% Carl Zeiss labor 36% 18% 7% Cymer Increase farm-out of R&D to knowledge institutes Suppliers will operate more like OEM s with their own R&D ASML will concentrate more on system architecture and integration Total R&D in the network more than 700 M in 2009 Slide 18 Public

19 ASML and its network has a highly trained workforce 49% of personnel have Advanced Degrees, of which approximately 200 PhD s 33% of personnel has Bachelor as highest degree R&D: >1,800 payroll + >900 contracted Integrated knowledge network: approximately another 20,000 jobs More than 600 suppliers compete to offer the best technology first 100% 90% Education levels 80% 70% 60% 50% 40% 30% Various < Bachelor Bachelor Advanced Degrees 20% 10% 0% ASML worldwide ASML Netherlands Development and Engineering Research Slide 19 Slide 19 Public

20 Integrated knowledge network essential for success OEM partners providing key sub systems R&D Partners (our virtual research lab) Resist Track Wafer scanner Masks Others Semiconductor device manufacturers Slide 20 Slide 20 Public

21 Top 20 spenders are ASML customers - they invest approx. 80% of industry capex Slide 21 Public

22 Agenda ASML Overview Technology Leadership Critical Mass through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 22 Public

23 Communication became ~ more energy efficient enabled by scaling of semiconductors 5 MJ/b 20 wood sticks of 2 cm diameter and 50 cm long equals ~3 dm³ Message size 10 characters or 10 ~15 MJ/dm³ energy from burning wood we use 45 MJ/message or 5 MJ/b Frederic Remington, The Smoke signal, 1905, Amon Carter Museum, Forth Worth, USA 1 μj/b High Speed Downlink Packet Access, HSDPA speed 3.65 Mb/s using 5.5 W resulting in ~1μJ/b (Siemens UR5 router) Slide 23 Public

24 Less energy to use a bit Computations per Kilowatt hour double every 1.5 years 1.E+16 1.E+15 1.E laptops SiCortex SC5832 Dell Dimension 2400 Gateway P MHz Computations per kwh 1.E+13 1.E+12 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 Univac I Eniac EDVAC Cray 1 supercomputer DEC PDP-11/20 SDS 920 Univac II IBM PC Univac III (transistors) IBM PS/2E + Sun SS1000 IBM PC-AT IBM PC-XT Commodore 64 Dell Optiplex GXI 486/25 and 486/33 Desktops Regression results: N = 76 Adjusted R-squared = Comps/kWh = exp( x year ) Average doubling time (1946 to 2009) = 1.57 years Source: Jonathan Koomey, Lawrence Berkeley National Laboratory and Stanford University, 2009 Slide 24 Public

25 Total energy to create the smallest chip function Total energy bill per memory bit continues to fall sharply with introduction of EUV 1000 Energy used to produce a memory bit [μj / bit ] NAND Introduction of EUV 10 0 Technology node [nm] Slide 25 Public

26 Litho investment per transistor decreases Litho cost falls 2.1% point/year faster than IC revenues per transistor 10,000,000 IC Revenue & Lithography investments per trillion transistors 1,000,000 CAGR: - 39,2% [USD per tr. transistors] 100,000 10,000 CAGR: - 41,3% 1, IC revenue per tr. Transisitors Expon. (IC revenue per tr. transisitors) Litho inv per tr. Transistors Expon. (Litho inv per tr. transistors) Sources: VLSI Research ( ) Slide 26 Slide 26 Public

27 Consumers are the winners $2,305 for 1Gigabyte (GB) 1000 $/GByte $0.17 for 1 GB Note: data isupply, March High quality Flash Slide 27 Public

28 Agenda Technology World Leadership in Europe Critical Mass in Manufacturing through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 28 Public

29 An accelerated roadmap forces litho complexity Lithography supports shrink roadmap Resolution/half pitch, "Shrink" [nm] AT:1200 XT:1400 XT:1700i DRAM (working memory in PC s) XT:1900i NXT:1950i Logic (microprocessors, the brains of PC s) NXE:3100 NAND Flash (special memory, used in, for example mp3 players) ARF ARFi 20 NXE:3300 EUV Year of production start* *Average customer input, update Jan 10 Slide 29 Public

30 Litho challenges and likely lithographic options k 1 = (half-pitch) * numerical aperture / wavelength Most likely Opportunity Challenge λ (nm) Half pitch (nm) NA Year Low k 1 > 0.25 challenge Double (Double) patterning, DP: CoO challenge DP, k 1 > DP², k 1 > Infrastructure challenge 0.33 With 248 nm 68 nm L&S With EUV 28 nm L&S With 193 nm DPT 22 nm L&S Slide 30 Public

31 Likely lithographic options k 1 = (half-pitch) * numerical aperture / wavelength Most likely Opportunity Challenge λ (nm) Half pitch (nm) NA Year Low k 1 > 0.25 challenge Double (Double) patterning, DP: CoO challenge DP, k 1 > DP², k 1 > Infrastructure challenge 0.33 With 248 nm 68 nm L&S With EUV 28 nm L&S With 193 nm DPT 22 nm L&S Slide 31 Public

32 ASML s R&D focus is on three strategic programs TWINSCAN NXT Holistic Lithography EUV Slide 32 Public

33 TWINSCAN NXT:1950i ArFi Immersion Scanner for Double Patterning 30nm and smaller Productivity more than 175 wafers per hour Overlay less than 3 nm Slide 33 Public

34 ASML Immersion Extendable Product Roadmap improved CD and overlay control at > 200 W/hr productivity Available Available Available Q Q XT:1900Gi XT:1950Hi NXT:1950i NXT:1950i+PEP NXT:1950i+EXT Resolution 40 nm 38 nm 38 nm 38 nm 38 nm CDU <1.5 nm <1.5 nm <1.1 nm <1.1 nm <0.8 nm Overlay (SMO 1 ) 6 5 nm (DCO²) 3.5 nm (DCO²) 2.5 nm (DCO²) 2.5 nm (DCO²) 2 nm Throughput W/hr 148 W/hr W/hr 200 W/hr 200 W/hr Defects/W 3 < Performance enhancements 1) Segmented wafer table 2) Improved optics 1950 lens 3) Air drag immersion hood 4) Faster stages Platform enhancements 1) New high-acceleration stages 2) Grid plate stage position measurement Field upgradeable ¹SMO: Single Machine Overlay ²DCO: Dedicated Chuck Overlay ³ASML Patterned defect test Slide 34 Slide 34 Public

35 Holistic Litho provides a window to shrink Process Window Process Control Pre-production: enlarges the process window further and earlier through pattern optimization and scanner tuning Production: ensures that the process stays in the sweet spot of the process window maximized for the specific application at hand, increasing yield and tool availability Slide 35 Public

36 Holistic Litho Addressing process control To keep process in application specific window center using computational lithography, cost effective metrology and feedback loops Data Scanner settings design/ mask data SMO FlexRay Tuning Scanner settings Wafer data Wafer data BaseLiner Control Scanner settings Data Scanner settings Value to Customers: Higher Product Yield Faster time to market for new chip designs Slide 36 Public

37 EUV for 22nm and beyond pilot systems to ship starting in H with volume production tools in 2012 Machine design changes Mirror optics and wafers in vacuum Moving stages in vacuum New type of light source Slide 37 Public

38 EUV Lithography: getting the light through Only 68% of the light will reflect from every mirror (maximum = 72%) scattering Mirror Mirror 0.3nm Mirror Flatness: 1mm over 1000 km 30cm Slide 38 Public

39 EUV Lithography: positioning of the light EUV mirror system km Mirror positioning 0,03 nm Overlay tolerance mirror: 0,1 nm Focus tolerance mirror: 25 nm Design examples Slide 39 Public

40 EUV - next generation lithography First NXE:3100 systems planned to ship in H th order received confirms appetite from all semiconductor sectors Slide 40 Public

41 EUV is the only feasible litho technology for foundries Enabling cost effective shrink without design restriction Relative litho cost per wafer DP EUV DDL SP DP, Double Patterning, good shrink, cost too DDL, high and Double design Dipole Lithography, restrictions. Extreme low k1 imaging at relaxed half pitch using double exposure and extreme EUV: the SMO. best balance Best cost between but major cost, shrink design restrictions and absence and of not design the most restrictions, aggressive however shrink major technology adoption hurdle Single layer patterning cost target Source TSMC, Prague 2009 Slide 41 Public

42 Litho costs back to normal with EUV >100 W/hr DPT case, Litho cost increases 2 ~ 3 times EUV case, Litho cost trend returns Litho cost per wafer [a.u.] st Gen. DTP 2 st Gen. DTP KrF set 1400 set 1900i set 1900i DPT 1900i DPT EUV 100W/hr EUV 180W/hr Source Samsung, Prague, oct 2009 Slide 42 Public

43 TWINSCAN EUV Product Roadmap Source roadmap in place for immersion compatible productivity Demonstration tool NXT:3100 NXE:3300B NXE:3300C Resolution 32 nm 27 nm 22 nm 16* nm NA / σ 0.25 / / / / OAI Overlay (SMO) < 7 nm < 4.5 nm < 3.5 nm < 3 nm Throughput W/hr 4 W/hr 60 W/hr 125 W/hr 150 W/hr Source 5 mj/cm 2, ~8 W 10 mj/cm 2, >100 W 15 mj/cm 2, >250 W 15 mj/cm 2, >350 W Main improvements 1) New EUV platform: NXE 2) Improved low flare optics 3) New high sigma illuminator 4) New high power source 5) Dual stages Main improvements 1) New high NA 6 mirror lens 2) New high efficiency illuminator 3) Off-axis illumination optional 4) Source power increase 5) Reduced footprint Platform enhancements 1) Off-Axis illumination 2) Source power increase * Requires <7 nm resist diffusion length Slide 43 Slide 43 Public

44 Extendibility of EUV down to sub 5 nm possible increasing apertures up to 0.7, wavelength reduction down to 6.8 nm using 13 nm compatible optics with depth of focus as the major challenge Resolution, Depth of focus [nm] Year Slide 44 Public k-factor, Aperture Resolution DOF@13 nm DOF@6.8 nm

45 Summary Semiconductor technology proliferation in all products has been fueled by the reduction of: energy used by devices energy to create devices cost to execute a calculation cycle or store/read a bit The cost of lithography relative to chip revenues is falling The model of a cooperative knowledge network between semiconductor producers, suppliers and technology partners is required to improve R&D effectiveness The current immersion tools continue to improve, using a holistic approach enabling double patterning down to 20 nm half pitch. Shrinking significantly beyond 20 nm using double patterning is a major challenge Long term, EUV is the only cost effective litho solution; its momentum will result in multiple tools proliferating into the market starting 2010 and enabling shrink for the next 15 years Slide 45 Public

46 Agenda Technology World Leadership in Europe Critical Mass in Manufacturing through Integrated Network The Sustainable Semiconductor Industry The Lithography Roadmap Market/ASML Update Slide 46 Public

47 Semiconductor revenue outlook increases 21% revenue growth, 15% IC unit growth* 2010 Semiconductor revenue growth forecast over time 30% 25% 20% 15% 10% 5% 0% Jan-09 Feb-09 Mar-09 Apr-09 May-09 Jun-09 Jul-09 Aug-09 Sep-09 Oct-09 Nov-09 Dec-09 Jan-10 Feb-10 Mar-10 Apr-10 May-10 Jun-10 Jul-10 Aug-10 Sep-10 Oct-10 Nov-10 Dec-10 YoY Semiconductor revenue growth [%] Sources: See chart (03/2010) *IC unit growth is average based on multiple industry analysts Slide 47 Public Future Horizons SIA Semico Dataquest IC Insights WSTS isuppli VLSI Research AVERAGE

48 IC inventories appear under control as measured by days of inventory mma IC unit sales, inventory and inventory days monthly IC inventory based on 3mma IC ASPs 3mma IC unit sale 3mma IC unit sales corrected for inventory Inventory days (right axis) Jan-01 Jul-01 Jan-02 Jul-02 Jan-03 Jul-03 Jan-04 Jul-04 Jan-05 Jul-05 Jan-06 Jul-06 Jan-07 Jul-07 Jan-08 Jul-08 Jan-09 Jul-09 Jan-10 3mma IC unit sales / Inventory [Bio. Units] IC inventory [days] - Source: VLSI Research, WSTS, ASML Last data point: February 2010 Slide 48 Public

49 WaferOutput[30mequiv.KWSM] By end 2010 memory output capacity is estimated to be more than 10% below peak capacity of 2008 Starts / Month [300mm equiv. KWspM] Memory WW wafer output split by wafer size and node Strong Capacity Add Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Source: ASML Marketing (9/09) 6x & 5x Conversion mm including(7x nm- 2x nm) 200mm (including 9xnm and 8x nm) Slide 49 Public 300mm utilisation & fab closures 200mm retirement Estimate Immersion for 5x, 4x & 3x conversion

50 Leading Edge Memory Drives Backlog Total value M 2,170 Technology 51% NXT 39% XT End-use Memory 75% IDM 14% Foundry 11% ArF immersion 90% KrF 9% i-line 1% Taiwan 31% USA 19% Region Korea 23% Japan 11% Singapore 6% Europe 3% China 7% Numbers have been rounded for readers convenience Slide 50 Public

51 Bookings activity by sector - Total value 1,004 M Q1 bookings are driven by DRAM with NAND order activity starting Foundry and IDM s ordering for capacity expansion Bookings in value Bookings in units Memory 79% Memory 48% Foundry 14% Foundry 30% IDM 7% IDM 22% Slide 51 Public

52 DRAMdemand&suply [Mio.GB] DRAMSuficiency [%] DRAM bit sufficiency analysis: At 47% bit demand growth market is slightly under-supplied during 2010 DRAM DRAM Sufficiency Model: ASML's fcst-based Supply versus Gartner-based Demand ASML Modeled DRAM bit supply [Mio. GB] Gartner Forecast DRAM bit demand [Mio. GB] DRAM Sufficiency (ASML) 140% 120% % % % % % 0 1Q08 2Q08 3Q08 4Q08 1Q09 2Q09 3Q09 4Q09 1Q10 2Q10 3Q10 4Q10 0% Slide 52 Public

53 NANDdemand&suply [Mio.GB] NANDSuficiency [%] NAND bit sufficiency analysis: At 70% bit demand growth market is well balanced for 2010 NAND 4,000 3,500 3,000 NAND Sufficiency Model: ASML's fcst-based Supply versus Gartner-based Demand ASML Modeled NAND bit supply [Mio. GB] Gartner Forecast NAND bit demand [Mio. GB] NAND Sufficiency (ASML) 160% 140% 120% 2, % 2,000 80% 1,500 60% 1,000 40% % 0 1Q08 2Q08 3Q08 4Q08 1Q09 2Q09 3Q09 4Q09 1Q10 2Q10 3Q10 4Q10 0% Slide 53 Public

54 2010 outlook Q2 Net sales expected around 1 billion Q2 bookings are expected at similar level as in Q ( 1,004 M) We expect this cycle to be sustained by the normal technology transitions of the early adopters, the subsequent technology conversions by second tier DRAM makers, the next Flash memory upgrade cycle anticipated for Q2 2010, as well as Foundry s structural capacity build at advanced nodes At current rate, WW litho systems sold in 2010 will be adding approx. 15% IC unit production capacity to the market. This controlled capacity increase supports the possibility of sustained growth in 2011 if IC unit growth continues per historical trend ASML on track to surpass our 2007 revenue peak of 3.8 billion in 2010 Slide 54 Public

55 Summary ASML has gained required scale through market gains supporting required litho R&D investments ASML is leading in meeting the industry's shrink roadmaps Memory supply/demand close to balance in Bits growth supplied by shrink only Further memory bit supply growth in near future will come from wafer supply growth ie. new fabs Slide 55 Public

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