Lithography on the Edge

Transcription

1 Lithography on the Edge David Medeiros IBM Prague, Czech Republic 3 October 009

2 An Edge A line where an something begins or ends: A border, a discontinuity, a threshold

3 Scaling Trend End of an Era? 0000 lambda / NA (nm) Year

4 Edge of a new era? 0000 lambda / NA (nm) NA EUV Year

5 An Edge A line where an something begins or ends: A border, a discontinuity, a threshold A favorable margin: An advantage, a benefit What are the challenges of patterning at the edge of the optical lithography capabilities? What are the implications of trying to move the edge, as with double patterning (DPL)? What innovations are at our disposal to give us an edge in meeting these challenges?

6 Double Patterning We are on the threshold of extending the utility of ArF litho for logic applications with DPL, which poses challenges in: Achieving process tolerances for complex designs Overlay CDU Maintaining reasonable mask count More importantly, overall CoO Opportunities Litho with an Edge Litho-Litho-Etch (LLE) Drive down CoO SMO (Source Mask Optimization) Make the most of k

7 Edge Placement Not an Issue of Demonstration We know we can print very small Can we meet tolerances? yield? profit? Edge Placement Error How accurately can we print a given set of features? (CD) How precisely can we control the variability of these features (CDU: DoF/EL) How accurately & precisely can we place features together to make useful structures? (OL) 56 nm Pitch via DPL

8 Double Patterning Overlay Requirements Sidewall Image Transfer (SIT) aka Self-Aligned Double Patterning (SADP) Effective Overlay ~4-9 nm required E CDU l Effective OL or IP dictated by Litho CDU & Dep/Etch Uniformity CDU s Spacer film E Sidewall Image Transfer Pitch Split Double Patterning (Resist-on-Resist) Overlay ~ 3-6 nm required CDU has significant OL contribution CDU l CDU s L L L L Pitch Split Double Patterning For example: A.J. Hazelton, et al. Double-patterning requirements for Optical lithography and prospects for optical extension without Double patterning, JMMM 8() 009

9 Overlay 4 nm overlay (3σ) in a 5 mm field = 60 ppb Plant Cell Width ~ 0 µm Petrin Tower, Prague ~ 60 m

10 Overlay Scanner manufacturing have made significant strides in overlay control Dedication may impact throughput but affords manufacturability Tooling is only part of the equation Mask Contributions: Image Placement Systematic, often correctable Nonsystematic Reticle Chucking Offsets Nonsystematic Process Induced Deformations Matched Machine Overlay Single Machine Overlay Dedicated Chuck Overlay

11 Overlay Control in DPL Driving down to manufacturable levels by removal of correctable systematics 0 X Mean Y Mean X Mean +3S Y Mean +3S Overlay Error (nm) Wafer num Experiment Experiment Best-Known-Method Ref: S. Holmes, et al, SPIE (009) See also: V. Nagaswami, et al, this conference

12 Two Primary Line/Space Patterning Methods Sidewall Image Transfer (SIT) Litho- Freeze -Litho-Etch st Litho Spacer Dep Etch st Litho. Freeze: Chemical or Thermal nd Litho nd Litho. Etch Benefits: CDU, Overlay Insensitive Challenges: Design Flexibility*, CoO Etch Benefits: Design Flexibility* Challenges: Overlay Sensitivity, CoO

13 Sidewall Image Transfer Complex decomposition, coloring challenges for D cases Trim layer becomes a challenge as well M. Burkhardt et al., EIPBN (009)

14 Pitch Split Double Exposure Initial target pitch is beyond resolution of.35na Optical Scanners After decomposition into separate exposures, the pattern can be imaged using new Double Patterning resist systems. M. Burkhardt et al., EIPBN (009)

15 CD Uniformity with Optimized Freeze Develop (Steps & ) st Litho only ARX98JN IBM Develop Avg: 30.9nm 3sigma:.55nm Min: 9.3nm Max: 3.3nm Measured 39 fields st Litho + Freeze ARX98JN after Freeze with FZX Avg: 8.8nm 3sigma:.57nm Min: 6.9nm Max: 30.8nm Comparable CDU before and after Freeze S. Holmes, et al, SPIE (009)

16 Intra-field CD before and after DoseMapper Optimization (Steps -3) Level Intrafield CD Pre DoseMapper Level Mean CD: 36. nm 3 Sigma:.3 nm Level Mean CD: 34.9 nm 3 Sigma:. nm Level Intrafield CD Post DoseMapper Level Mean CD: 36.8 nm 3 Sigma:.5 nm Level Mean CD: 34.4 nm 3 Sigma: 0.7 nm S. Holmes, et al, SPIE (009)

17 Aerial Images for Off-Axis Illumination Vertical Feature Horizontal Feature k = Dipole Contrast is highest at low k, but can t print wrong orientation at pitch Quadrapole prints intermediate structures well but not dense pitch. Annular prints multiple orientation but has limited contrast at dense pitch.

18 Sensitivity IBM Research of Division Illuminator & Systems and at Technology Active Level: Group D Effects Even a pitches greater than minimum, dipole suffers from wrong-way ringing, as predicted C-Quad allows for improved dual-orientation as well as D printability, but limits pitch M. Colburn, et al. SPIE (009)

19 Printing Wrong Way Gate with Dipole Illuminator: D H-Bar H-Bar: Driving Poly to tight pitch compromises wrong-way printability RET must be balanced to accommodate ACLV, WW, Density M. Colburn, et al. SPIE (009)

20 Double Dipole Litho (DDL) for D Printing (not DPL). Y-dipole exposure. Layout Design 4. Single Developed Image in Resist 3. X-dipole exposure DDL affords increased degree of freedom in the optimization of the print image by separation of design into two masks that generate an image within a single resist. The sum of the aerial image results in enhanced resolution not afforded by a conventional -mask imaging solution. M. Burkhardt, PMJ 006

21 Scaling Trend: Design Restrictions Shrink of linewidth of pitch imparts a shrink of CD uniformity specification Image quality needs to improve from one generation to the next Dipole illumination yields close to perfect imaging for one linewidth/pitch combination. May be the only option to achieve desired CD uniformity and line edge roughness This implies either unidirectional design / preferred orientation of critical levels or mask proliferation What are the implications for optimized illumination for each orientation in a design?

22 Mask Count Hypothetical, for Illustrative Purposes Level Solution Active Gate 3 Contact 4 Metal 5 Via 6 Metal 7 Via 8 Metal 3 9 Via 3 45 nm 3 nm nm U nm R 5 nm U 5 nm R nm R SE SE* SE/DE* SE/DE* DPL/SIT DPL/SIT DPL/SIT Metal Total for 0 Crit. Levels ! 8 33!!

23 Mask Count Hypothetical, for Illustrative Purposes Level Solution Active Mask Count for 0 Critical Levels Gate Via Via Via Contact 0 Metal 5 Metal 0 5 Metal 3 Metal Total for 0 Crit. Levels 45 nm SE nm SE* nm U SE/DE* Another discontinuity! Logic Node nm R SE/DE* nm U DPL/SIT ! 0 5 nm R DPL/SIT nm R DPL/SIT !!

24 Process Steps / CoO Mask Count is only one part of the cost of ownership equation Different products require different ground rules: e.g., MPU (HP) vs. Mobile (LP) Depending on wafers/mask, mask count can either be huge component of CoO or relatively small Increased complexity and added process steps are always concerns Double patterning adds wafer passes on expensive litho clusters Adds to the etch, deposition, cleans, etc Adds to the metrology burden (non-value add costs increase) Added capacity adds to capital demands Added steps add to the propensity for yield detractors, defectivity Cost effective solutions are required that preclude need for mask & process complexity Litho-litho-etch Source mask optimization

25 Source Mask Optimization (SMO) SMO applies intensive optimization to the fundamental degrees of freedom in the system Source Goal is to find the best set of image-forming waves that can propagate through the exposure tool Wavefront Engineering No starting mask or source: only the target & manufacturability tolerances are required. Manufacturable Masks Mask Wavefronts Seek the globally optimum set of imageforming waves (incl. multiple exposures) within constraints (NA, PV, mask ) Create manufacturable masks from the result T. Inoue, NGL Japan, 009 Design

26 SMO Example: Contact Level Design source Measured source Design Layout Mask Design Mask Wafer Simulation Wafer D. Gil, PMJ, 009 & T. Inoue, NGL Japan, 009

27 IBM Research Division & Systems and Technology Group (k ~0.8) Applications for low k Single Exposure 40 nm Brick wall nm SRAM M (0.0 µm) 40 nm : L/S Horizontal Simulation Vertical On Wafer 6th International Symposium on Immersion Lithography Extensions

28 Illuminator Trend Conventional Stock Diffractive Optical Elements (DOE) Split Exposures with Multiple Stock DOEs or Custom Parametric Conventional DOE Custom Free Form DOE Free Form Source via Programmable Illuminator

29 Flexray First Image: SE nm SRAM First Metal Rendered Source DOE Wafer Flexray Source Flexray Wafer Target Aerial Image nm SRAM M (0.00 µm ) min 90 nm pitch min 40 nm CD >00 nm DoF See also: F. de Jong, ASML, this conference

30 Summary We are entering into a new regime of patterning where unprecedented control in CDU & OL is required to meet process tolerances Design implications balanced with economics (cost of ownership) will dictate DPL use model and in turn to level of complexity required Solutions will differ depending on product / market demands Innovations in materials, process controls and computational methods should provide the necessary tools to extend ArF lithography for logic to the 5 nm node.

31 Acknowledgements M. Burkhardt, S. Burns, M. Colburn, D. Corliss, A. Gabor, D. Gil, T. Farrell, G. Han, T. Inoue, K. Lai, S. Halle, S. Holmes, S. Mansfield, G. McIntyre, J. Meiring, D. Melville, A. Rosenbluth, K. Tian, G. Gomba ASML, JSR, KLA-Tencor, Mentor Graphics, TEL, Zeiss Alliance Partners & SUNY Albany Portions of this talk are from work performed by the Research Alliance Teams at various IBM Research and Development Facilities

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