Decomposition difficulty analysis for double patterning and. the impact on photomask manufacturability

Transcription

1 Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability Yuichi Inazuki 1*, Nobuhito Toyama, Takaharu Nagai 1, Takanori Sutou 1, Yasutaka Morikawa 1, Hiroshi Mohri 1 and Naoya Hayashi 1 Martin Drapeau 3, Kevin Lucas 4 and Chris Cork 5 1 Dai Nippon Printing Co, Ltd., --1 Fukuoka, Fujimino , Japan DNP Corp. USA, 335 Kifer Road, Suite 1, Santa Clara, CA 9551, USA 3 Synopsys Inc., One Antares Dr., Nepean, Ontario KE 8C4, Canada 4 Synopsys Inc., 131 S. Mopac Expressway, Austin, TX 78746, USA 5 Synopsys Inc., 1 Rue Lavoisier, Montbonnot, 3833 France *Phone: FAX: inazuki_y@mail.micro.dnp.co.jp ABSTRACT Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond while conventional single exposure () is still dominant with hyper NA avoiding DPT difficulties such as split-conflict or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and small latitude of lithography and photomask fabricated with much tight specification are required for. Then there must be double patterning (DP) approach even for available resolution. In this paper DP for available resolution is evaluated on lithography performance, pattern decomposition, photomask fabrication and inspection load. DP includes pattern pitch doubled of, then lithography condition such as mask error enhancement factor (MEEF) is less impacted and the lower MEEF means less tight specification for photomask fabrication. By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And also this software detects split-conflicts such as triangle or square placement from contact spacing. For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared. Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result, there are few differences of defect sensitivity for only dense features and also few differences of false defect counts between and DP with less NA. But if higher NA used, DP s inspection sensitivity is able to be lowered Then inspection load for DP would be lighter than. Keywords: Double patterning, Decomposition, photomask inspection, mask error enhancement factor Design for Manufacturability through Design-Process Integration II, edited by Vivek K. Singh, Michael L. Rieger, Proc. of SPIE Vol. 695, 6951O, (8) X/8/$18 doi: / SPIE Digital Library -- Subscriber Archive Copy Proc. of SPIE Vol O-1

2 1. Introduction Double Patterning Lithography (DPL) has been thought the most practical candidate technologies for 45nm half-pitch (HP) or beyond and ITRS6-update defined the specification of DPL [1]. The main concerns and issues of DPT were also reported [] that overlay and CD uniformity would be critical because they impact wafer CD directly. On the other hand, the resolution with optical lithography tool has been improved since water immersion was introduced and already reached NA: 1.35 [3]. There are issues even if hyper NA in the case of close to the region of the resolution limit [4]. The contrast with the region on wafer will decreases and MEEF will grow. The recent study shows MEEF grows around.8 at 9nm pitch with NA: 1.35 of Binary-mask [5]. This makes photomask specification tighter at the region. If the pitch will be doubled, the MEEF will descend to around 1.5. This means CD error on photomask impacts over 1.8x for 9nm pitch to compared to 18nm pitch. Then DP or ideal pitch doubling will have opportunities to help such tight photomask specification. There are still issues remaining for DP as split-conflict. The split-conflict means the pattern disable to be split into pitch doubled. This conflict from non DP oriented design, but recent checking or decomposition software detects those conflicts in early stage and decomposes the design into optimized two complements.. Motivation The supposed critical pitch at 3nm-node poly layer is around 1nm. When current exposure technologies are applied to the pitch, enough contrast for lithography is not obtained by conventional off-axis illumination (OAI) such as annular illumination. Then stronger OAI such as Cquad illumination will achieve enough contrast though strong OAI causes OPC difficult due to high complex degree of coherence [6]. In this situation, the pitch doubled as DPT enables to apply annular illumination which impacts less OPC and improves DOF of complex pattern (shown in Fig.1). As to critical pitch, sub resolution assist feature (SRAF) is available to be placed and so almost equivalent DOF with is achieved. These optical behaviors with those illuminations are estimated with 3D simulation. Strong OAI impacts two-dimensional features such as line-ends or corners than lines. Comparing line-end simulation with NA1.35/Cquad for 1nm pitch and NA1./Annular for nm shows the Cquad illumination grows line-end shortening almost x larger than Annular at 6nm defocus. And the line-ends is around 1.5x shrank even if at focal (shown in Fig.). Proc. of SPIE Vol O-

3 + pitch1n pitchn Mask Cquad Annular Annular Fig.1: Description of critical pattern and illumination setting of and DP Design & Contour example Line-end gap Line shrinking CD deviation (a) Line-end shortening (b) Line shrinking 18-6nm defocus 16 Just focus 14 6nm defocus S6 S8 S1 S6 S8 S1 S6 S8 S1 S6 S8 S1 Line-end gap Line-end gap Line-end gap Line-end gap NA1.35 cquad NA1. annular CD deviation [nm@1x] NA1.35 cquad NA1. annular Fig.: CD-defocus and Proximity effect comparison of and DP illumination (a) Line-end shortening (b) Line shrinking Proc. of SPIE Vol O-3

4 From photomask fabrication point of view, DPT is concerned to lead yield loss by tight image placement or CD control. As same as writing, inspection constitutes large portion of whole photomask fabrication. In this research, photomask inspection will be invested. When there are all 1nm pitch pattern for and nm pitch with SRAF for DP, mask inspection load of DP is supposed to be as heavy as that of because of almost same number of features. On the other hand, MEEF of DP is almost.8x smaller than that of (shown in Fig.3). And it is around.6x when DP is applied with NA1.35 as well. In this situation, smaller MEEF will reduce not only the tight specification of mask CD but sensitivity of defect printing, and these reductions mean improving photomask fabrication latitude. Then photomask inspection is tried using test pattern of DP and on same plate. Those patterns were prepared with Synopsys decomposition and OPC tool. 3.5 MEEF MEEF NA1.35 NA1. NA1.35 cquad annular annular Fig.3: MEEF comparison of and DPT illumination 3. Experimental This experimental consists of data-prep, photomask fabrication and the evaluation. The concept of this experiment is to evaluate mask fabrication load, especially inspection load of DP pattern at 3nm-node poly layer. (1). Design preparation: Decomposition and OPC In this research, test circuit pattern is prepared by Synopsys Inc. Synopsys DPT software goals is optimizing polygon cutting for DPT in designs, reducing design rework & optimize layout area, maximizing output symmetry & density uniformity and wafer yield such as OPC friendly & overlay-aware decomposition, DPT-aware OPC & RET and accurate litho, etch & substrate modeling. Currently Synopsys decomposition and coloring are based on Proteus model-based OPC platform. (). Estimating writing load and inspection load Conventional photomask fabrication load is estimated by counting the number of writing figures. Writing time is almost Proc. of SPIE Vol O-4

5 proportional to the number of writing features for variable shaped beam writer. Then comparison of writing load of DPL and will be helpful to estimating the load and the cost for DPL. And also supposed inspection load will be estimated by counting the number of MRC. (3). Mask inspection In this section, one binary mask with and DP data is fabricated with leading-edge writing tool and is inspected for experimentally estimating inspection load. Inspection conditions are shown as follows; Mask: Binary (NTAR7) Pattern Data: Simple L/S and line-end pattern with programmed defect OPCed circuit pattern prepared by Synopsys (area: um x 15um) Inspection tool: TeraScanHR (KLA-Tencor), 7nm pixel, Transmitted light mode, Die to Database, Die to Die CD 1% evaluation tool: AIMS45-193i (Carl Zeiss), scanner mode (): 1.35NA, Cquad.9/.6/3deg, X/Y pol. (DP): 1. or 1.35NA, Annular.9/.6, X/Y pol. (3-1). Programmed defect to calibrate inspection sensitivity Generally, high sensitivity to detect small defects and reduction of false defects are trade-off. For the conventional criteria, inspection sensitivity should be adjusted to detect the defect that causes CD variation of more than 1% or so of CD and higher sensitivity is not required to reduce detecting false defect counts. To calibrate the inspection sensitivity, programmed defect for both and DP are created. Some of them are convex defect in lines and line-end extension (shown in Fig.4). Convex defect Line-end oversize Convex defect DP Line-end oversize Fig.4: Description of test pattern for setting inspection sensitivity (3-). Checking false counts with circuit pattern As known well, currently inspection capability is nearly limit to 3nm-node because of small pattern size and tight pitch on photomask. The degradation of inspection image will causes increasing false defects. When mask inspection is done, Proc. of SPIE Vol O-5

6 large number of false defect is a big problem that a lot of time is spent confirming image review. If higher inspection sensitivity is required and this sensitivity creates large number of false defect, it will be the region of inspection is impossible. Then circuit data of and DP without defect is inspected to check false counts. 4. Result and Discussion (1). Decomposition results Sample of logic poly layer were split (shown in Fig.5). There are no software-induced conflicts and stitching is treated to be less impact at critical (gate) region. And there are results of split sample logic contact and routing metal (shown in Fig.6). At contact region, this software detects split-conflicts such as triangle or square placement from contact distance. At high density metal region, similar density of each data and no split error are found. These represent Synopsys DPT decomposition software is ready for production. Fig.5: Split sample of logic poly (a) (b) l E -III- E -III- E -I- U LU L H I n n E E H U n I I I Fig.6: Split sample of (a) logic contact (b) routing metal U H Proc. of SPIE Vol O-6

7 (). Estimating writing load and inspection load Writing load and inspection load was estimated by computing approach or counting the number of each data (shown in Fig.7). DP s number of fractured data is 1.3x of sum of s. DP s tough aspect is not only tight image placement but writing time. On the other hand, DP s MRC error is.4x of s. As to DP s inspection, false counts or inspection load will be reduced (shown in Fig.8 (a)). But if MRC rule is tighter, there is no difference between and DP. 1.3x DP1 DP DP1 + DP # of fractured data Fig.7: number of fractured data Line error (a) Space error DP1 DP (b) DP1 + DP Line error Space error.4x # of MRC error # of MRC error Fig.8: (a) MRC results (b) tighter MRC results (3-1). calibrating inspection sensitivity From the programmed defect of various defect size and AIMS evaluation, proper sensitivity for inspection tool is fixed to achieve enough sensitivity and to detect less false counts. From these experiments, the sensitivity of NA1.35/ and NA1./DP is almost same. This sensitivity means same inspection load for higher NA/ and less NA/DP. And in the case of NA1.35DP, the 8% less sensitivity achieves same NA/ (shown in Fig.9). Proc. of SPIE Vol O-7

8 6 AIMS CD CD 1% variation Defect size [nm] Fig.9: AIMS CD vs. Defect size (1. NA Cquad) DP (1. NA annular) DP (1.35 NA annular) (3-). False counts with circuit pattern In this experiment, DP s inspection sensitivity was set for 1.NA. Biased pattern is meant as Mean-To-Target (MTT) error or mask CD variation of OPC target. As a result, there are - false counts at DP pattern, otherwise 1-7 false counts at pattern (shown in Fig.1 (a), (b)). From these results, it is possible to apply 45nm-node inspection tool to DP. And also it is not impossible for depending on adjusting inspection conditions. As trials increased, some worse results in DP s condition were found. So in this approach, mask inspection load in the particular case is considered as heavy as s (shown in Fig.1 (c)). Proc. of SPIE Vol O-8

9 # of False counts # of False counts DP1 DP (a) bias -8 bias 8 Mask bias on mask scale [nm] (c) DP1 DP #1 # #3 #4 #5 #6 #7 #8 Trial number # of False counts (b) bias -8 bias 8 Mask bias on mask scale [nm] DP1 DP Fig.1: inspection results of circuit pattern. (a) Die to Database results with bias variation (b) Die to Die results with bias variation (c) Die to Database results of 8 times trial (4). Photomask fabrication load In terms of MEEF, when pattern decomposition reduces MEEF, OPC s parameter setting have to be changed while this experimental employing same condition for both DP and. The OPC condition tuning will help to reduce photomask fabrication load for DP. From the computational result, DP s number of fractured data is 1.3x of sum of s due to more SRAF requirement. Fabrication load for writing time is tougher than. (4.1). Photomask inspection load As well as fabrication load, smaller MEEF have to lead less sensitivity of defect printing. There are few differences of the sensitivity of defect printing between and DP for only dense features due to the DP s condition. In terms of false Proc. of SPIE Vol O-9

10 defect, there are also few differences between and DP. But if higher NA used that reduces MEEF of critical pattern, DP s inspection sensitivity is able to be lowered. Then inspection load for DP is lighter than. 5. Summary - MEEF of DP is.8x smaller than for logic 3nm-node furthermore.6x smaller if 1.35NA used - DPL decomposition software is ready for production - DP mask fabrication load is heavier for writing - Less inspection sensitivity is applicable for DP but not that reduces false counts if higher NA used for DP - DP for available condition is confirmed as one option for logic 3nm-node 6. Probe Further Whole DPL flow will be confirmed. - decomposing practical 3nm node design & OPC - verifying mask fabrication & inspection load 7. Acknowledgement Authors would like to specially thanks to co-workers in Synopsys & DNP who supported data preparation or mask fabrication. Imai-san in DNP who supported and advised us about mask inspection. References: 1. itrs6 : public.itrs.net or etc.. M. Dusa, et. al. "Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets", Proc. of SPIE, Vol. 65 (7) 3. J. Klerk, et al, "Performance of a 1.35NA ArF immersion lithography system for 4nm applications", Proc. of SPIE, Vol.65 (7) 4. J. Park, et al, "Application Challenges with Double Patterning Technology (DPT) beyond 45nm", Proc. of SPIE, Vol.6349 (6) 5. T. Adachi, et al, "45-3nm node photomask technology with water immersion lithography", Proc. of SPIE, Vol (6) 6. K. Lucas, et al, "Patterning control budgets for the 3nm generation incorporating lithography, design and RET variations", Proc. of SPIE, Vol. 65 (7) Proc. of SPIE Vol O-1