Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung-Kai Chen, Albert Li

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung-Kai Chen, Albert Li"

Transcription

1 Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung-Kai Chen, Albert Li Design Service Division, GLOBAL UNICHIP CORP., Taiwan, ROC Xiaopeng Dong, Vassilios Gerousis, Miles Zhang, Yanling Weng, Rose Li IC Design Group, Cadence Design Systems, San Jose, USA Notice of Copyright This material is protected under the copyright laws of the U.S. and other countries and any uses not in conformity with the copyright laws are prohibited. Copyright for this document is held by the creator authors and sponsoring organizations of the material, all rights reserved. This document has been submitted to, and reviewed and posted by, the editors of DAC.com. Please recycle if printed.

2 Page 2 of 8 ARTICLE: Early Substrate Noise Estimation Fast Estimation and Mitigation of Substrate Noise in Early Design Stage for Large Mixed Signal SOCs Shi-Hao Chen, Hsiung Kai Chen, Albert Li Design Service Division, GLOBAL UNICHIP CORP., Taiwan, ROC Xiaopeng Dong, Vassilios Gerousis, Miles Zhang, Yanling Weng, Rose Li IC Design Group, Cadence Design Systems, San Jose, USA Abstract Making devices smarter and smaller requires the ability to put the entire system on a single chip, where digital and analog design blocks are all integrated on a single chip substrate. Just as timing, die size and power must be considered and addressed in the design, the interdependence of analog and digital must also be properly handled. One of the most significant design challenges is that of signal integrity, where noise caused by digital switching inside the digital section couples through the common substrate and impacts the functionality of analog blocks [1]. It is commonly understood that sensitive analog blocks should be separated from digital blocks, with additional protection required. Modern tools insert guard rings around sensitive blocks, but this increases die size and cost. To address substrate noise coupling and mitigate the substrate noise impact to analog blocks in the early stages of design is an even more challenging task. Obviously, addressing substrate noise coupling in the prototyping stage has the potential to greatly improve quality of silicon and shorten time to market. The difficulties lie in the modeling and characterization of digital switching noise, the fast extraction of substrate, the fast propagation of substrate noise at full-chip scale, and the mitigation of substrate noise based on these analyses. This article describes a substrate analysis and mitigation flow based on the Cadence Encounter Digital Implementation (EDI) system, along with results obtained for a large mixed-signal design in TSMC 90nm process technology. The EDI substrate noise analysis capabilities afford mixed-signal designers the ability to run simulation, observe VCO noise and determine guidelines for the digital block implementation. Additional details will be presented at the 2010 DAC User Track. Index Terms Substrate noise, noise-aware floorplan guidance and mitigation, mixed-signal design prototyping.

3 Page 3 of 8 I. INTRODUCTION The foundation for the contribution reported in this article (and in the forthcoming 2010 DAC User Track) consists of a substrate noise-aware implementation methodology and underlying tool capabilities. Figure 1 illustrates how substrate noise is caused by digital switching inside the digital section, coupled through the common substrate to impact the functionality of analog blocks. Digital VDD in out Digital GND Analog GND N+ P+ P+ N+ N+ P+ P+ N+ N+ N-Well Digital P-Substrate Analog Figure 1: Substrate noise through common substrate. Figure 2: Substrate noise-aware implementation flow. Figure 2 shows three stages of the design flow where substrate noise analysis (SNA) can be performed. The first stage is early in the implementation, when the floorplan and power plan are ready. The second opportunity to perform SNA is after placement and routing. The third stage is after fullchip implementation has been completed, when the designer must extract the full-chip noise model and run simulation to verify whether the IP has the potential to fail. This last analysis is part of systemlevel co-simulation, in that a P/G package model is needed for accurate analysis. At the third stage, because timing and power are fixed, more detailed analysis results accurate parasitics, clean

4 Page 4 of 8 constraints, etc. and hence more accurate SNA results are possible. In Figure 2, if there is too large a substrate noise value after the floorplan and power planning stage, we would need to change our design in stage A to meet the design criteria. If there is a large substrate noise value after placement and routing, we can reduce this in stage A or B. And, if we have a large substrate noise value after timing and power have been closed, we can mitigate this in stage B or C. Changing the design in a later stage entails greater effort to finish (close) the design. Another available solution to fix substrate noise is to add a guard ring around sensitive analog blocks or noise sources. Although some tools exist for characterization of substrate noise, these tools are normally targeted to later design stages and used for analog IP characterization. These tools also lack the capacity to handle large mixed-signal ICs. In general, there are four issues that must be solved in order to overcome the substrate noise problem for large mixed signal ICs: 1) digital noise characterization; 2) substrate modeling and substrate noise estimation; 3) evaluation of analog IPs in the light of substrate noise; and 4) substrate noise prevention. Dynamic Rail Analysis Substrate Noise Analysis Figure 3: Substrate noise analysis step. Figure 4: Tile model correlation. The substrate noise aware implementation flow shown in Figure 3 provides solutions to all the above four issues. Dynamic rail analysis is used to compute the digital noise injection. In the early design stage, even with partial data, designers can utilize a tool such as Cadence s ERA (early rail analysis) to perform dynamic rail analysis for digital noise injection characterization. The flow also uses the concept of a tile model and a tile model pre-characterization approach. This makes substrate

5 Page 5 of 8 modeling and noise estimation easier to accomplish in an implementation flow. The tile model can be extracted using tools such as Cadence QRC RF, based on the foundry s process design kit (PDK). Validation against golden tools such as QRC RF using test structures has been performed, with good results. (QRC RF has been silicon-qualified on advanced process nodes at various foundries.) Figure 4 shows the quality of correlation between the tile model based analysis and QRC RF. The difference is within 2dB even through distances up to 2000um. With respect to substrate noise analysis (SNA), three major capabilities are provided. (1) The first capability is the intuitive noise contour map which helps designers to handle the many different design aspects that impact substrate noise. A substrate constraint file can help bring characterized noise tolerance information into this design flow. (2) The second capability is for floorplan guidance. In applying the substrate noise aware implementation flow at early design stage, we have demonstrated how a substrate noise contour map can be computed and used as a guide for floorplan exploration and DC source assignments. (3) The third capability involves a virtual guard ring. By exploiting the ability to estimate guard ring impact on substrate noise, we have created a technique whereby the tool is used to determine the width of a guard ring that would help to maximize the noise reduction while preserving as much chip area as possible. Beyond generating a substrate noise contour map, the tool can also provide FFT-based frequency analysis for propagated noise waveforms and noise source waveforms. Designers can relate the noise to required noise tolerance at specific frequencies. Preliminary Power Planning Power-aware DFT Power planning Power Switch Placement Planning VCD pattern Timing Window 1st Placement power analysis Auto-fixing No Meet? Yes CTS/Post-route Meet VCD pattern Timing Window 2nd power analysis Traditional Flow Simulation-free Dynamic IR Prediction Static/Transient Power Analysis No Meet? Yes Meet Decap insertion lengthy loop Decap insertion Power SwitchOpt. Power Domain Check (UPDC) CTS/Post-route Timing Optimization Figure 5: Dynamic IR prevention. Because substrate noise results are highly related to dynamic rail results, dynamic IR prevention can also help to reduce substrate noise. Reference [2] proposes a dynamic IR prevention flow to improve chip yield. Figure 5 shows a complete solution for dynamic IR prevention. II. SUMMARY OF RESULTS A large mixed-signal design based on TSMC 90nm process has been used to validate our flow and methodology. The design goal is to mitigate substrate coupling for the sensitive on-chip analog IPs, especially the PLL blocks. The design parameters that can be adjusted are floorplan, DC source location, and guard ring. The reported results are obtained using the Cadence EDI system including

6 Page 6 of 8 EPS and ERA for dynamic rail analysis and EDI SNA for substrate noise analysis. All results that we discuss in the following are generated for this testcase design implemented in TSMC 90nm process. Table 1 shows testcase parameters. All runtimes correspond to a 2.6GHz AMD dual-core Opteron with 16G memory. Table 1 Testcase Parameters. Process TSMC 90nm LP Die Size 3700um x 3700um Instance count 100K VDD/VSS Power/Ground Nets VDDA/VSSA VDDD/VSSD QRC RF [1] is a golden analysis tool for substrate noise. Table 2 shows that EDI SNA and QRC RF have almost the same runtime for substrate noise analysis. However, EDI SNA can handle a larger design size than QRC RF. Due to runtime (turnaround time), we do not use QRC RF for chiplevel substrate analysis. Table 2 Runtime Comparison. EDI SNA QRC RF Size 100K Cells 3.6K devices Run Time 135 minutes 120 minutes Clean room for analog block Noisy region Figure 6: Low substrate noise impact in dotted circle. (a) Max substrate Noise Value: mV Max dynamic IR drop value: 7.69% (b) Figure 7: (a) Substrate noise analysis result; (b) dynamic rail analysis result.

7 Page 7 of 8 Max substrate Noise Value: 59.91mV Max dynamic IR drop value: 5.25% Add DC source (a) (b) Figure 8: (a) Substrate noise analysis result; (b) dynamic rail analysis result with addition of one DC source in dotted circle. The first set of results demonstrate the generation of substrate noise contour map for the full chip including the impact of digital package, analog ground network and analog package loading. These are based on both EPS and ERA dynamic rail analysis results for digital noise injection, and show correlated substrate noise results (see Figure 6). The SNA contour map is useful for identifying quiet areas for possible analog block placement in the floorplan stage. The second set of results demonstrates floorplan improvement to mitigate the substrate noise as well as the use of DC sources to mitigate excessive noise injection due to ground bounce. Table 3 Dynamic IR and Substrate Noise Results for Figures 7 and 8. Fig. 7 Fig. 8 Max. IR drop 7.69% 5.25% Max. Substrate Noise 90.95mV 59.91mV We see that the power plan should be taken into account, since a better dynamic rail result corresponds to a better substrate noise result. In Figure 7, the worst/best locations of substrate noise are similar to these locations identified in the dynamic rail analysis. Table 3 summarizes the dynamic IR and substrate noise results of Figure 7 and Figure 8. PLL LDO LDO PLL Min noise: 64.3mV Max noise: 72.15mV Delta noise: 7.85mV (a) Min. noise: 59.41mV Max. noise: 77.12mV Delta noise: 17.71mV (b) Figure 9: (a) SNA result with old floorplan; (b) SNA result with new floorplan.

8 Page 8 of 8 Enlarge virtual guard ring (a) Noise (mv) The most efficient guard ring width Width (um) (b) Enlarge virtual guard ring (c) Figure 10: (a) Substrate noise result with 100um virtual guard ring width; (b) minimum substrate noise in with different virtual guard ring width; (c) substrate noise result with 10um virtual guard ring width. Figure 9 shows the change in worst dynamic rail results after changing the design floorplan. As noted above, the worst dynamic rail result has a strong correspondence to the worst substrate noise result. We observe that changing the floorplan might not improve the substrate noise result directly if the power grid design is bad (it may hurt the dynamic rail result). Table 4 summarizes the dynamic IR and substrate noise results of Figure 9, as well as the result of Figure 10(c) discussed in the following. Table 4 Dynamic IR and Substrate Noise Results for Figure 9. Fig. 9 (a) Fig. 9 (b) Fig. 10 (c) Max. IR Drop 7.69% 8.29% 7.69% Max. Substrate Noise 72.15mV 77.12mV 17.13mV Max. Substrate Noise 90.95mV 98.68mV 90.95mV A third set of results demonstrates the use of the virtual guard ring capability for area-effective reduction of substrate noise to sensitive IPs. A set of noise reduction curves against different loadings of observation points inside the virtual guard ring helps identify the tradeoff between substrate noise reduction and preservation of chip area resource (see Figure 10). III. CONCLUSION We have described a substrate noise-aware implementation flow that can be applied at a full-chip level. Floorplan guidance is provided at the prototype stage according to a substrate noise contour map. Because substrate noise is closely related to the dynamic rail result, we can reduce substrate noise by reducing dynamic rail noise. What-if analysis obtains a substrate noise result with a virtual guard ring, allowing determination of an effective guard ring width. Further, with pre-characterized noise sensitivity of a given analog block, the SoC designer may not need to feed the noise waveform to the analog block with time-consuming SPICE simulations. REFERENCES [1] A. Afzali-Kusha, M. Nagata, N. K. Verghese and D. J. Allstot, Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation, Proceedings of the IEEE 94 (2006), pp [2] S.-H. Chen, K.-C. Chu, J.-Y. Lin and C.-H. Tsai, DFM/DFY Practices During Physical Designs for Timing, Signal Integrity, and Power, Proc. Asia and South Pacific Design Automation Conference, 2007, pp [3] Cadence Design Systems, Inc., Parasitic Extraction and Postlayout Verification for RF/Wireless Designs, Workshop Manual, April 2007.

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Power-Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS -Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS Jiajun Shi, Mingyu Li and Csaba Andras Moritz Department of Electrical and Computer Engineering University of Massachusetts, Amherst, MA,

More information

Ruixing Yang

Ruixing Yang Design of the Power Switching Network Ruixing Yang 15.01.2009 Outline Power Gating implementation styles Sleep transistor power network synthesis Wakeup in-rush current control Wakeup and sleep latency

More information

Substrate Level Noise Analysis Tool (SNAT) in Mixed Signal circuits

Substrate Level Noise Analysis Tool (SNAT) in Mixed Signal circuits Substrate Level Noise Analysis Tool (SNAT) in Mixed Signal circuits Anish joseph Research Scholar Abstract: There exist several tools that can be used to predict the substrate noise profile of digital

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks

An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks Sanjay Pant, David Blaauw University of Michigan, Ann Arbor, MI Abstract The placement of on-die decoupling

More information

Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis

Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis Authors: Rick Brooks, Cisco, ricbrook@cisco.com Jane Lim, Cisco, honglim@cisco.com Udupi Harisharan, Cisco,

More information

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids

Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids Woo Hyung Lee Sanjay Pant David Blaauw Department of Electrical Engineering and Computer Science {leewh, spant, blaauw}@umich.edu

More information

Signal Integrity Modeling and Simulation for IC/Package Co-Design

Signal Integrity Modeling and Simulation for IC/Package Co-Design Signal Integrity Modeling and Simulation for IC/Package Co-Design Ching-Chao Huang Optimal Corp. October 24, 2004 Why IC and package co-design? The same IC in different packages may not work Package is

More information

A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20

A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20 A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20 Joseph Adut,Chaitanya Krishna Chava, José Silva-Martínez March 27, 2002 Texas A&M University Analog

More information

Signal Integrity Design of TSV-Based 3D IC

Signal Integrity Design of TSV-Based 3D IC Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues

More information

Relationship Between Signal Integrity and EMC

Relationship Between Signal Integrity and EMC Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?

More information

3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications

3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications 3D IC-Package-Board Co-analysis using 3D EM Simulation for Mobile Applications Darryl Kostka, CST of America Taigon Song and Sung Kyu Lim, Georgia Institute of Technology Outline Introduction TSV Array

More information

CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT

CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT CAPLESS REGULATORS DEALING WITH LOAD TRANSIENT 1. Introduction In the promising market of the Internet of Things (IoT), System-on-Chips (SoCs) are facing complexity challenges and stringent integration

More information

PDS Impact for DDR Low Cost Design

PDS Impact for DDR Low Cost Design PDS Impact for DDR3-1600 Low Cost Design Jack W.C. Lin Sr. AE Manager jackl@cadence.com Aug. g 13 2013 Cadence, OrCAD, Allegro, Sigrity and the Cadence logo are trademarks of Cadence Design Systems, Inc.

More information

Bootstrapped ring oscillator with feedforward inputs for ultra-low-voltage application

Bootstrapped ring oscillator with feedforward inputs for ultra-low-voltage application This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Bootstrapped ring oscillator with feedforward

More information

Multiple Reference Clock Generator

Multiple Reference Clock Generator A White Paper Presented by IPextreme Multiple Reference Clock Generator Digitial IP for Clock Synthesis August 2007 IPextreme, Inc. This paper explains the concept behind the Multiple Reference Clock Generator

More information

Emulating and Diagnosing IR-Drop by Using Dynamic SDF

Emulating and Diagnosing IR-Drop by Using Dynamic SDF Emulating and Diagnosing IR-Drop by Using Dynamic SDF Ke Peng *, Yu Huang **, Ruifeng Guo **, Wu-Tung Cheng **, Mohammad Tehranipoor * * ECE Department, University of Connecticut, {kpeng, tehrani}@engr.uconn.edu

More information

CS 6135 VLSI Physical Design Automation Fall 2003

CS 6135 VLSI Physical Design Automation Fall 2003 CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5

More information

Mixed Signal Virtual Components COLINE, a case study

Mixed Signal Virtual Components COLINE, a case study Mixed Signal Virtual Components COLINE, a case study J.F. POLLET - DOLPHIN INTEGRATION Meylan - FRANCE http://www.dolphin.fr Overview of the presentation Introduction COLINE, an example of Mixed Signal

More information

Appendix. RF Transient Simulator. Page 1

Appendix. RF Transient Simulator. Page 1 Appendix RF Transient Simulator Page 1 RF Transient/Convolution Simulation This simulator can be used to solve problems associated with circuit simulation, when the signal and waveforms involved are modulated

More information

Lecture 10. Circuit Pitfalls

Lecture 10. Circuit Pitfalls Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski

More information

Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters

Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters International Journal of Electronics and Electrical Engineering Vol. 2, No. 4, December, 2014 Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters Jefferson A. Hora, Vincent Alan Heramiz,

More information

DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers

DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers Muhammad Nummer and Manoj Sachdev University of Waterloo, Ontario, Canada mnummer@vlsi.uwaterloo.ca, msachdev@ece.uwaterloo.ca

More information

Low Noise Amplifier Design Methodology Summary By Ambarish Roy, Skyworks Solutions, Inc.

Low Noise Amplifier Design Methodology Summary By Ambarish Roy, Skyworks Solutions, Inc. February 2014 Low Noise Amplifier Design Methodology Summary By Ambarish Roy, Skyworks Solutions, Inc. Low Noise Amplifiers (LNAs) amplify weak signals received by the antenna in communication systems.

More information

Vishram S. Pandit, Intel Corporation (916) ]

Vishram S. Pandit, Intel Corporation (916) ] DesignCon 2008 Simulation and Characterization of GHz On-Chip Power Delivery Network (PDN) Vishram S. Pandit, Intel Corporation [vishram.s.pandit@intel.com, (916)356-2059] Woong Hwan Ryu, Intel Corporation

More information

Design and Analysis of a Second Order Phase Locked Loops (PLLs)

Design and Analysis of a Second Order Phase Locked Loops (PLLs) Design and Analysis of a Second Order Phase Locked Loops (PLLs) DIARY R. SULAIMAN Engineering College - Electrical Engineering Department Salahaddin University-Hawler Zanco Street IRAQ Abstract: - This

More information

Design and Analysis of a Portable High-Speed Clock Generator

Design and Analysis of a Portable High-Speed Clock Generator IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 4, APRIL 2001 367 Design and Analysis of a Portable High-Speed Clock Generator Terng-Yin Hsu, Chung-Cheng

More information

DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP

DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP DESIGN AND ANALYSIS OF LOW POWER CHARGE PUMP CIRCUIT FOR PHASE-LOCKED LOOP 1 B. Praveen Kumar, 2 G.Rajarajeshwari, 3 J.Anu Infancia 1, 2, 3 PG students / ECE, SNS College of Technology, Coimbatore, (India)

More information

The water-bed and the leaky bucket

The water-bed and the leaky bucket The water-bed and the leaky bucket Tim Williams Elmac Services Wareham, UK timw@elmac.co.uk Abstract The common situation of EMC mitigation measures having the opposite effect from what was intended, is

More information

Synthesis of Optimal On-Chip Baluns

Synthesis of Optimal On-Chip Baluns Synthesis of Optimal On-Chip Baluns Sharad Kapur, David E. Long and Robert C. Frye Integrand Software, Inc. Berkeley Heights, New Jersey Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou and Bigchoug

More information

STM RH-ASIC capability

STM RH-ASIC capability STM RH-ASIC capability JAXA 24 th MicroElectronic Workshop 13 th 14 th October 2011 Prepared by STM Crolles and AeroSpace Unit Deep Sub Micron (DSM) is strategic for Europe Strategic importance of European

More information

Proposed DPWM Scheme with Improved Resolution for Switching Power Converters

Proposed DPWM Scheme with Improved Resolution for Switching Power Converters Proposed DPWM Scheme with Improved Resolution for Switching Power Converters Yang Qiu, Jian Li, Ming Xu, Dong S. Ha, Fred C. Lee Center for Power Electronics Systems Virginia Polytechnic Institute and

More information

THE TREND toward implementing systems with low

THE TREND toward implementing systems with low 724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 7, JULY 1995 Design of a 100-MHz 10-mW 3-V Sample-and-Hold Amplifier in Digital Bipolar Technology Behzad Razavi, Member, IEEE Abstract This paper

More information

DesignCon Design of a Low-Power Differential Repeater Using Low Voltage and Charge Recycling. Brock J. LaMeres, University of Colorado

DesignCon Design of a Low-Power Differential Repeater Using Low Voltage and Charge Recycling. Brock J. LaMeres, University of Colorado DesignCon 2005 Design of a Low-Power Differential Repeater Using Low Voltage and Charge Recycling Brock J. LaMeres, University of Colorado Sunil P. Khatri, Texas A&M University Abstract Advances in System-on-Chip

More information

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems Mikhail Popovich and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester, Rochester,

More information

ASIC Computer-Aided Design Flow ELEC 5250/6250

ASIC Computer-Aided Design Flow ELEC 5250/6250 ASIC Computer-Aided Design Flow ELEC 5250/6250 ASIC Design Flow ASIC Design Flow DFT/BIST & ATPG Synthesis Behavioral Model VHDL/Verilog Gate-Level Netlist Verify Function Verify Function Front-End Design

More information

10 GHz Voltage Controlled Ring Oscillator for High Speed Application in 130nm CMOS Technology

10 GHz Voltage Controlled Ring Oscillator for High Speed Application in 130nm CMOS Technology Australian Journal of Basic and Applied Sciences, 6(8): 17-22, 2012 ISSN 1991-8178 10 GHz Voltage Controlled Ring Oscillator for High Speed Application in 130nm CMOS Technology FatemehTaghizadeh-Marvast,

More information

Exploring the Basics of AC Scan

Exploring the Basics of AC Scan Page 1 of 8 Exploring the Basics of AC Scan by Alfred L. Crouch, Inovys This in-depth discussion of scan-based testing explores the benefits, implementation, and possible problems of AC scan. Today s large,

More information

This work is supported in part by grants from GSRC and NSF (Career No )

This work is supported in part by grants from GSRC and NSF (Career No ) SEAT-LA: A Soft Error Analysis tool for Combinational Logic R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin Microsystems Design Laboratory, Penn State University (ramanara, jskim, vijay,

More information

Variation-Aware Design for Nanometer Generation LSI

Variation-Aware Design for Nanometer Generation LSI HIRATA Morihisa, SHIMIZU Takashi, YAMADA Kenta Abstract Advancement in the microfabrication of semiconductor chips has made the variations and layout-dependent fluctuations of transistor characteristics

More information

Changing the Approach to High Mask Costs

Changing the Approach to High Mask Costs Changing the Approach to High Mask Costs The ever-rising cost of semiconductor masks is making low-volume production of systems-on-chip (SoCs) economically infeasible. This economic reality limits the

More information

Energy Efficient and High Speed Charge-Pump Phase Locked Loop

Energy Efficient and High Speed Charge-Pump Phase Locked Loop Energy Efficient and High Speed Charge-Pump Phase Locked Loop Sherin Mary Enosh M.Tech Student, Dept of Electronics and Communication, St. Joseph's College of Engineering and Technology, Palai, India.

More information

PAPER Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

PAPER Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise 1948 IEICE TRANS. FUNDAMENTALS, VOL.E94 A, NO.10 OCTOBER 2011 PAPER Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise Takaaki OKUMURA, a) and Masanori HASHIMOTO, Members

More information

Resonant Clock Design for a Power-efficient, High-volume. x86-64 Microprocessor

Resonant Clock Design for a Power-efficient, High-volume. x86-64 Microprocessor Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor Visvesh Sathe 1, Srikanth Arekapudi 2, Alexander Ishii 3, Charles Ouyang 2, Marios Papaefthymiou 3,4, Samuel Naffziger 1 1

More information

MDLL & Slave Delay Line performance analysis using novel delay modeling

MDLL & Slave Delay Line performance analysis using novel delay modeling MDLL & Slave Delay Line performance analysis using novel delay modeling Abhijith Kashyap, Avinash S and Kalpesh Shah Backplane IP division, Texas Instruments, Bangalore, India E-mail : abhijith.r.kashyap@ti.com

More information

The wireless industry

The wireless industry From May 2007 High Frequency Electronics Copyright Summit Technical Media, LLC RF SiP Design Verification Flow with Quadruple LO Down Converter SiP By HeeSoo Lee and Dean Nicholson Agilent Technologies

More information

Agilent Combining Network and Spectrum Analysis and IBASIC to Improve Device Characterization and Test Time

Agilent Combining Network and Spectrum Analysis and IBASIC to Improve Device Characterization and Test Time Agilent Combining Network and Spectrum Analysis and IBASIC to Improve Device Characterization and Test Time Application Note 1288-1 Using the 4396B to analyze linear and non-linear components - a 900 MHz

More information

FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase Locked Loop

FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase Locked Loop IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase

More information

DAT175: Topics in Electronic System Design

DAT175: Topics in Electronic System Design DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

AN-1370 APPLICATION NOTE

AN-1370 APPLICATION NOTE APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com Design Implementation of the ADF7242 Pmod Evaluation Board Using the

More information

CHAPTER. delta-sigma modulators 1.0

CHAPTER. delta-sigma modulators 1.0 CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly

More information

Aarthi.P, Suresh Kumar.R, Muniraj N. J. R, International Journal of Advance Research, Ideas and Innovations in Technology.

Aarthi.P, Suresh Kumar.R, Muniraj N. J. R, International Journal of Advance Research, Ideas and Innovations in Technology. ISSN: 2454-132X Impact factor: 4.295 (Volume3, Issue6) Available online at www.ijariit.com Implementation of Pull-Up/Pull-Down Network for Energy Optimization in Full Adder Circuit P. Aarthi Assistant

More information

CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL

CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL IEEE INDICON 2015 1570186537 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 60 61 62 63

More information

An Area efficient structure for a Dual band Wilkinson power divider with flexible frequency ratios

An Area efficient structure for a Dual band Wilkinson power divider with flexible frequency ratios 1 An Area efficient structure for a Dual band Wilkinson power divider with flexible frequency ratios Jafar Sadique, Under Guidance of Ass. Prof.K.J.Vinoy.E.C.E.Department Abstract In this paper a new design

More information

ENGAT00000 to ENGAT00010

ENGAT00000 to ENGAT00010 Wideband Fixed Attenuator Family, DIE, DC to 50 GHz ENGAT00000 / 00001 / 00002 / 00003 / 00004 / 00005 / 00006 / 00007 / 00008 / 00009 / 00010 Typical Applications ENGAT00000 to ENGAT00010 Features Space

More information

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits P. S. Aswale M. E. VLSI & Embedded Systems Department of E & TC Engineering SITRC, Nashik,

More information

In the previous chapters, efficient and new methods and. algorithms have been presented in analog fault diagnosis. Also a

In the previous chapters, efficient and new methods and. algorithms have been presented in analog fault diagnosis. Also a 118 CHAPTER 6 Mixed Signal Integrated Circuits Testing - A Study 6.0 Introduction In the previous chapters, efficient and new methods and algorithms have been presented in analog fault diagnosis. Also

More information

Strategies for High Density and High Speed Packaging. Ride the Wave Workshop

Strategies for High Density and High Speed Packaging. Ride the Wave Workshop Strategies for High Density and High Speed Packaging Ride the Wave Workshop Topics! Trends in Packaging! Common Design Challenges! Design through Software! Supply Plane Analysis with SIwave! Non-ideal

More information

Engineering the Power Delivery Network

Engineering the Power Delivery Network C HAPTER 1 Engineering the Power Delivery Network 1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? The power delivery network consists of all the interconnects in the power supply path

More information

Implementing a Voltage Scaling Reference Flow Based on ARM s IEM. Giorgio Parapini Cadence ICD Product Engineer

Implementing a Voltage Scaling Reference Flow Based on ARM s IEM. Giorgio Parapini Cadence ICD Product Engineer Implementing a Voltage Scaling Reference Flow Based on ARM s IEM Giorgio Parapini Cadence ICD Product Engineer Abstract Relative to ARM's IEM technology, this session describes a reference flow to implement

More information

An alternative approach to model the Internal Activity of integrated circuits.

An alternative approach to model the Internal Activity of integrated circuits. An alternative approach to model the Internal Activity of integrated circuits. N. Berbel, R. Fernández-García, I. Gil Departament d Enginyeria Electrònica UPC Barcelona Tech Terrassa, SPAIN nestor.berbel-artal@upc.edu

More information

Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs

Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs Transceiver Portfolio Workshops 2009 Question What is Your PDN Design Methodology? Easy Complex Historical Full SPICE simulation

More information

A SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer

A SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer A SiGe 6 Modulus Prescaler for a 6 GHz Frequency Synthesizer Noorfazila Kamal,YingboZhu, Said F. Al-Sarawi, Neil H.E. Weste,, and Derek Abbott The School of Electrical & Electronic Engineering, University

More information

Ground-Adjustable Inductor for Wide-Tuning VCO Design Wu-Shiung Feng, Chin-I Yeh, Ho-Hsin Li, and Cheng-Ming Tsao

Ground-Adjustable Inductor for Wide-Tuning VCO Design Wu-Shiung Feng, Chin-I Yeh, Ho-Hsin Li, and Cheng-Ming Tsao Applied Mechanics and Materials Online: 2012-12-13 ISSN: 1662-7482, Vols. 256-259, pp 2373-2378 doi:10.4028/www.scientific.net/amm.256-259.2373 2013 Trans Tech Publications, Switzerland Ground-Adjustable

More information

UNEXPECTED through-silicon-via (TSV) defects may occur

UNEXPECTED through-silicon-via (TSV) defects may occur IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 36, NO. 10, OCTOBER 2017 1759 Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs Young-woo

More information

Electrical Characterization of a 64 Ball Grid Array Package

Electrical Characterization of a 64 Ball Grid Array Package EMC Europe - Hamburg, 8 th September 008 Summary Electrical Characterization of a 64 Ball Grid Array A. Boyer (), E. Sicard (), M. Fer (), L. Courau () () LATTIS - INSA of Toulouse - France () ST-Microelectronics

More information

Making your ISO Flow Flawless Establishing Confidence in Verification Tools

Making your ISO Flow Flawless Establishing Confidence in Verification Tools Making your ISO 26262 Flow Flawless Establishing Confidence in Verification Tools Bryan Ramirez DVT Automotive Product Manager August 2015 What is Tool Confidence? Principle: If a tool supports any process

More information

From IC characterization to system simulation by systematic modeling bottom up approach

From IC characterization to system simulation by systematic modeling bottom up approach From IC characterization to system simulation by systematic modeling bottom up approach Frédéric Lafon, François de Daran VALEO VIC, Rue Fernand Pouillon, 944 Creteil Cedex, France, frederic.lafon@valeo.com

More information

Statistical Static Timing Analysis Technology

Statistical Static Timing Analysis Technology Statistical Static Timing Analysis Technology V Izumi Nitta V Toshiyuki Shibuya V Katsumi Homma (Manuscript received April 9, 007) With CMOS technology scaling down to the nanometer realm, process variations

More information

Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)

Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN) Indonesian Journal of Electrical Engineering and Computer Science Vol. 5, No. 3, March 2017, pp. 643 ~ 649 DOI: 10.11591/ijeecs.v5.i3.pp643-649 643 Current Steering Digital Analog Converter with Partial

More information

A Resonance-Free Power Delivery System Design Methodology applying 3D Optimized Extended Adaptive Voltage Positioning.

A Resonance-Free Power Delivery System Design Methodology applying 3D Optimized Extended Adaptive Voltage Positioning. A Resonance-Free Power Delivery System Design Methodology applying 3D Optimized Extended Adaptive Voltage Positioning Tao Xu Brad Brim Agenda Adaptive voltage positioning (AVP) Extended adaptive voltage

More information

A 45-nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O

A 45-nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O A 45-nm SOI-CMOS Dual-PLL Processor Clock System for Multi-Protocol I/O Dennis Fischette, Alvin Loke, Michael Oshima, Bruce Doyle, Roland Bakalski*, Richard DeSantis, Anand Thiruvengadam, Charles Wang,

More information

Non-linear Control. Part III. Chapter 8

Non-linear Control. Part III. Chapter 8 Chapter 8 237 Part III Chapter 8 Non-linear Control The control methods investigated so far have all been based on linear feedback control. Recently, non-linear control techniques related to One Cycle

More information

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure

More information

A Low Power Single Phase Clock Distribution Multiband Network

A Low Power Single Phase Clock Distribution Multiband Network A Low Power Single Phase Clock Distribution Multiband Network A.Adinarayana Asst.prof Princeton College of Engineering and Technology. Abstract : Frequency synthesizer is one of the important elements

More information

Innovations in EDA Webcast Series

Innovations in EDA Webcast Series Welcome Innovations in EDA Webcast Series August 2, 2012 Jack Sifri MMIC Design Flow Specialist IC, Laminate, Package Multi-Technology PA Module Design Methodology Realizing the Multi-Technology Vision

More information

An Example Design using the Analog Photonics Component Library. 3/21/2017 Benjamin Moss

An Example Design using the Analog Photonics Component Library. 3/21/2017 Benjamin Moss An Example Design using the Analog Photonics Component Library 3/21/2017 Benjamin Moss Component Library Elements Passive Library Elements: Component Current specs 1 Edge Couplers (Si)

More information

Power Integrity Analysis of AVR Processor

Power Integrity Analysis of AVR Processor Power Integrity Analysis of AVR Processor Master of Science (MSc) Thesis in Integrated Electronic System Design BADRI NARAYANAN RAVI Chalmers University of Technology Department of Computer Science and

More information

An Ultra Low Power Successive Approximation ADC for Wireless Sensor Network

An Ultra Low Power Successive Approximation ADC for Wireless Sensor Network Internatıonal Journal of Natural and Engineering Sciences 7 (2): 38-42, 213 ISSN: 137-1149, E-ISSN: 2146-86, www.nobel.gen.tr An Ultra Low Power Successive Approximation ADC for Wireless Sensor Network

More information

Research Article Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA

Research Article Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA Active and Passive Electronic Components Volume 213, Article ID 96757, 5 pages http://dx.doi.org/1.1155/213/96757 Research Article Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA Neeta Pandey

More information

DDR4 memory interface: Solving PCB design challenges

DDR4 memory interface: Solving PCB design challenges DDR4 memory interface: Solving PCB design challenges Chang Fei Yee - July 23, 2014 Introduction DDR SDRAM technology has reached its 4th generation. The DDR4 SDRAM interface achieves a maximum data rate

More information

Low Skew CMOS PLL Clock Drivers

Low Skew CMOS PLL Clock Drivers Low Skew CMOS PLL Clock Drivers The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide

More information

Lecture 17. Low Power Circuits and Power Delivery

Lecture 17. Low Power Circuits and Power Delivery Lecture 17 Low Power Circuits and Power Delivery Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2007 Ron Ho and Mark Horowitz w/ slides used from David Ayers 1 Power Delivery

More information

Active Decap Design Considerations for Optimal Supply Noise Reduction

Active Decap Design Considerations for Optimal Supply Noise Reduction Active Decap Design Considerations for Optimal Supply Noise Reduction Xiongfei Meng and Resve Saleh Dept. of ECE, University of British Columbia, 356 Main Mall, Vancouver, BC, V6T Z4, Canada E-mail: {xmeng,

More information

ML12202 MECL PLL Components Serial Input PLL Frequency Synthesizer

ML12202 MECL PLL Components Serial Input PLL Frequency Synthesizer MECL PLL Components Serial Input PLL Frequency Synthesizer Legacy Device: Motorola MC12202 The ML12202 is a 1.1 GHz Bipolar monolithic serial input phase locked loop (PLL) synthesizer with pulse swallow

More information

Improving the immunity of sensitive analogue electronics

Improving the immunity of sensitive analogue electronics Improving the immunity of sensitive analogue electronics T.P.Jarvis BSc CEng MIEE MIEEE, I.R.Marriott BEng, EMC Journal 1997 Introduction The art of good analogue electronics design has appeared to decline

More information

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh

Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh Abstract A 5GHz low power consumption LNA has been designed here for the receiver front end using 90nm CMOS technology.

More information

Design of a Tri-modal Multi-Threshold CMOS Switch with Application to Data Retentive Power Gating

Design of a Tri-modal Multi-Threshold CMOS Switch with Application to Data Retentive Power Gating Design of a Tri-modal Multi-Threshold CMOS Switch with Application to Data Retentive Power Gating Ehsan Pakbaznia, Student Member, and Massoud Pedram, Fellow, IEEE Abstract A tri-modal Multi-Threshold

More information

Chapter 13: Comparators

Chapter 13: Comparators Chapter 13: Comparators So far, we have used op amps in their normal, linear mode, where they follow the op amp Golden Rules (no input current to either input, no voltage difference between the inputs).

More information

Power Optimization Techniques Using Multiple VDD

Power Optimization Techniques Using Multiple VDD Power Optimization Techniques Using Multiple VDD Presented by: Rajesh Panda LOW POWER VLSI DESIGN (EEL 6936-002) Dr. Sanjukta Bhanja Literature Review 1) M. Donno, L. Macchiarulo, A. Macii, E. Macii and,

More information

Digital Integrated Circuits Perspectives. Administrivia

Digital Integrated Circuits Perspectives. Administrivia Lecture 30 Perspectives Administrivia Final on Friday December 14, 2001 8 am Location: 180 Tan Hall Topics all what was covered in class. Review Session - TBA Lab and hw scores to be posted on the web

More information

Bridging the Gap between Dreams and Nano-Scale Reality

Bridging the Gap between Dreams and Nano-Scale Reality Bridging the Gap between Dreams and Nano-Scale Reality Ban P. Wong Design Methodology, Chartered Semiconductor wongb@charteredsemi.com 28 July 2006 Outline Deficiencies in Boolean-based Design Rules in

More information

CROSS-LAYER DESIGN FOR QoS WIRELESS COMMUNICATIONS

CROSS-LAYER DESIGN FOR QoS WIRELESS COMMUNICATIONS CROSS-LAYER DESIGN FOR QoS WIRELESS COMMUNICATIONS Jie Chen, Tiejun Lv and Haitao Zheng Prepared by Cenker Demir The purpose of the authors To propose a Joint cross-layer design between MAC layer and Physical

More information

A New Phase-Locked Loop with High Speed Phase Frequency Detector and Enhanced Lock-in

A New Phase-Locked Loop with High Speed Phase Frequency Detector and Enhanced Lock-in A New Phase-Locked Loop with High Speed Phase Frequency Detector and Enhanced Lock-in HWANG-CHERNG CHOW and NAN-LIANG YEH Department and Graduate Institute of Electronics Engineering Chang Gung University

More information

The Design of a Two-Stage Comparator

The Design of a Two-Stage Comparator The Design of a Two-Stage Comparator Introduction A comparator is designed with the specifications provided in Table I. Table II summarizes the assumptions that may be made. To meet the specifications,

More information

CLASS-C POWER AMPLIFIER DESIGN FOR GSM APPLICATION

CLASS-C POWER AMPLIFIER DESIGN FOR GSM APPLICATION CLASS-C POWER AMPLIFIER DESIGN FOR GSM APPLICATION Lopamudra Samal, Prof K. K. Mahapatra, Raghu Ram Electronics Communication Department, Electronics Communication Department, Electronics Communication

More information

Characterization and Variation Modeling for 22FDX. Ning Jin Digital Design Methodology Team

Characterization and Variation Modeling for 22FDX. Ning Jin Digital Design Methodology Team Characterization and Variation Modeling for 22FDX Ning Jin Digital Design Methodology Team Agenda 1 2 3 4 Introduction to 22FDX Technology Library Characterization in Liberate and Variety Library Characterization

More information

ECE3204 D2015 Lab 1. See suggested breadboard configuration on following page!

ECE3204 D2015 Lab 1. See suggested breadboard configuration on following page! ECE3204 D2015 Lab 1 The Operational Amplifier: Inverting and Non-inverting Gain Configurations Gain-Bandwidth Product Relationship Frequency Response Limitation Transfer Function Measurement DC Errors

More information

Simulation and Modeling of Capacitive Coupling Interconnection For 3D Integration

Simulation and Modeling of Capacitive Coupling Interconnection For 3D Integration 2012 4th International Conference on Computer Modeling and Simulation (ICCMS 2012) IPCSIT vol.22 (2012) (2012) IACSIT Press, Singapore Simulation and Modeling of Capacitive Coupling Interconnection For

More information