Litho Metrology. Program

Transcription

1 Litho Metrology Program John Allgair, Ph.D. Litho Metrology Manager (Motorola assignee) Phone: January, 2004 National Nanotechnology Initiative Workshop on Instrumentation and Metrology for Nanotechnology

2 Outline International Technology Roadmap for Semiconductors Litho Metrology Challenges Summary 01/20/2004 John Allgair Slide 2

3 ITRS: International Technology Roadmap for Semiconductors The ITRS includes the roadmap for emerging NanoTechnology and Electronics. The ITRS is sponsored by the Semiconductor Industry Association (SIA), the European Electronic Component Association (EECA), the Japan Electronics & Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA) International SEMATECH is the global communication center for this activity. The ITRS team also coordinates the USA region events. 01/20/2004 John Allgair Slide 3

4 ITRS Challenge for Metrology In-Time Metrology and Characterization Leading Production Technology Node = DRAM ½ Pitch nm 65 nm 45 nm 32 nm 22 nm 18 nm MPU / ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Leading Edge Tool Specifications set 32 nm Node Metrology R&D Materials available 10 nm structures difficult to obtain Beta Site 65 nm Node R&D 45 nm Node Early R&D 32 nm Node 01/20/2004 John Allgair Slide 4

5 ITRS Challenge New Materials and Structures Leading Production Technology Node = DRAM ½ Pitch 90nm 65 nm 45 nm 32 nm 22 nm 18 nm Driver MPU / ASIC ½ Pitch (nm) MPU MPU Printed Gate Length (nm) MPU MPU Physical Gate Length (nm) MPU 01/20/2004 John Allgair Slide 5

6 Messages from IC Industry In-Line Metrology must be linked to the Manufacturing Process Advanced Process Control and Advanced Equipment Control will be Necessary for NanoManufacturing Process Productivity Metrology for NanoElectronics will also be more than Dimensional and Mechanical Measurements Electrical Properties of materials and Electrical Parametrics of devices must be considered 01/20/2004 John Allgair Slide 6

7 Litho Metrology Challenges for Nanotechnology Critical dimension measurements Overlay control Film thickness measurements Defect control 01/20/2004 John Allgair Slide 7

8 Litho Metrology for Volume Manufacturing CD Control Starts at the Mask 22 nm Node Overlay and CD Control after Exposure 6.35mm 152mm 152mm 52 nm mask line width 26 nm scattering bars CD Control after Etch EUV 13 nm printed line width 9 nm physical line width 01/20/2004 John Allgair Slide 8

9 Investigate High Voltage CD-SEM High Voltage CD-SEM kev e- Comparison of conventional SE (left) and Low Loss (right) images of copper interconnects. Note the greatly enhanced surface detail and lack of edge brightness in the Low Loss image. Low loss detector Micrograph courtesy of O C Wells Figures from David Joy 01/20/2004 John Allgair Slide 9

10 Scatterometry for CD Measurements What are the Limits? Mirror Multi-wavelength Light Source Θ in = Θ out Real Time Calculation Polarization Sensitive Detector of line width & shape Eliminates Libraries Incident Polarized White Light 0th order /20/2004 John Allgair Slide 10 0

11 Opportunities for the distant future Electron Holography & Low Energy Electron Microscopy (LEEM) Point Projection Microscope LEEM screen reflected rays Y nanotip nanogun X bias New normal incidence David Joy, Univ. of TN Tromp and Reuter IBM Si(111) 01/20/2004 John Allgair Slide 11

12 Overlay Opportunities WAFERS/WK 5000 DIES/WAFER 1000 PRICE/DIE 5.00 COST/DIE nm Control Improvement Provides M$/Yr Revenue Opportunity 0 250nm 180nm 130nm 90nm 65nm 45nm Technology Generation 6nm 4nm 2nm 01/20/2004 John Allgair Slide 12 Offset Revenue Loss ($M/YR) Microeconomics of Overlay Control at the 65nm Technology Node ISSM, September 2003

13 Summary With relationship to the semiconductor industry, government funding for nanotechnology metrology needs to focus on technology requirements beyond the 32 nm node (10-15 years out) Key focus areas in litho metrology include techniques for measurement and control of critical dimensions, overlay, film thickness and defectivity 01/20/2004 John Allgair Slide 13

14 Author s Background John Allgair, Ph.D. has worked in the semiconductor industry for 13 years in a variety of areas including design, etch, films, lithography and metrology. Currently he is a Motorola assignee to International SEMATECH responsible for coordinating litho metrology programs to meet the requirements of the International Technology Roadmap for Semiconductors. Previously he was responsible for parametric and defect metrology technology development and manufacturing implementation for Motorola's Dan Noble Center. He is on the SPIE program committee for metrology and has been published in several industry journals. He has a Ph.D. in Electrical Engineering with an emphasis in semiconductor physics and processing from Arizona State University. His dissertation research was focused on e-beam lithography for the manufacture of single electron devices as part of the DARPA ULTRA electronics program. Prior to Motorola, he worked as a process engineer for ASM America and as a systems analyst for Allied Signal. 01/20/2004 John Allgair Slide 14