Managed Variability Present and Future of Design-Process Integration from 32nm to 22nm and beyond

Transcription

1 Managed Variability Present and Future of Design-Process Integration from 32nm to 22nm and beyond Luigi Capodieci, Ph.D. R&D Fellow Luigi DFM Capodieci, Ph.D. R&D Fellow Managed Variability and DFM

2 Outline: Variability Taxonomy of Variability Lithography Induced variability Mask, Proximity, Stepper, Resist, Wafer Design Effects, Mitigation Activities Other Process Induced Variability: Gate Dielectric, CMP, Stress, Thermal Impact of Variation: Random versus Systematic DFM: A systematic approach to managed variability Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 2

3 Outline: DFM A brief history of DFM Yield and Design Rules at 45, 32 and 22 nm Design For Manufacturability (DFM) Layout Printability Verification (across PW) Holistic Design Rules Selection/Optimization Towards Design Layout Regularity Advanced DFM Applications Conclusions: DFM enabling 22 nm and below Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 3

4 Variability Basics [I] At the limits of the geometric scaling roadmap : variability as a percentage of feature size increases: atoms don t scale kt/q doesn t scale photons don t scale Main factors: Intrinsic process variability Environmental effects Physical limits Variability affects Yield, Performance, and Power Variability can be classified as random and systematic Physical limits cause random variations (e.g. dopant fluctuations) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 4

5 Variability Basics [II] Variability occurs at different length scales Across a single transistor (or wire) Transistor to transistor Across Die Across Wafer Wafer to Wafer Lot to Lot Often systematic effects are considered random only because it is difficult (or impossible) to characterize them Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 5

6 Lithography related variability Scanner Design Mask/OPC Wafer Resist Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 6

7 dev Mask related variability Mask Process Etch and develop signatures Loading density dependent Mask Proximity Effects E-beam exposure noise Range: Stepper Field (across die), Gate-to Gate Magnitude: Total 5-10nm on mask (1.5-2nm on wafer) Linearities CD Target dense clear iso clear dense dark iso dark Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 7

8 OPC related variability OPC Errors, Model Accuracy, Algorithm Convergence Model Errors: Lead to systematic CD errors, e.g. through pitch OPC Convergence: Mask making limits or numerical errors lead to CD errors (quasi-random) Post OPC CD through pitch Range: Gate to Gate Systematic and random Magnitude: 2nm for restricted pitches, 5-10nm for all pitches Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 8

9 Wafer related variability Variation Across Scanner Field Causes: Focus Leveling, Dose Uniformity, Lens Aberrations (additional influence from mask) Range: Across Field (Across Die), Die to Die Systematic Magnitude: 1-2nm Top Right Die Shows Low CD Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 9

10 Resist related variability Line Edge Roughness (LER) CD Variation along Line Edge Dependent on resist type, resist processing, resist etch Range: Intra-Gate W=100nm Random Magnitude: depends on length scale, 1nm-3nm (1s) CD vs tgt (nm) W=1000nm CD vs tgt (nm) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 10

11 Edge Placement Error (nm) Edge Placement Error (nm) Design related variability Layout Regularity OPC can minimize CD variation at one focus position for different layout styles Range: Gate to Gate Magnitude: 3-5nm Both systematic and random Mitigation: Uniform Layout reduces CD variation through-focus Smaller Variation of Average CD Smaller Variation of CD range Conventional Layout Defocus (um) CD Variation Post-OPC (10,000 gates simulated) Restricted Design Rules Defocus (nm) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 11

12 CMP related variability Metal layers of modern submicron process are chemical-mechanically polished. CMP is a process that has all types of variations: Lot to lot (systematic) wafer to wafer (systematic) Within wafer (systematic) Within die (quasi-random) Except for some- within-die variations, all of these are uncorrelated from metal level to metal level Variations in thickness can be very significant, easily up to 50% variations in thickness and hence R and C However, essentially all of these variations are uncorrelated from layer to layer Moreover, R max correlates with C min, and vice versa: you never get the case of C max *R max or C min * R min R/um C/um RC/um^2 short nom tall nm fine pitch metal, arbitrary units Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 12

13 CMP variability mitigation: Tiling TILING Helps balancing low density regions & reducing standard deviation Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 13

14 Temperature related variability Variations in temperature can have significant impact on device performance and reliability W These variations can be very local (transistor self-heating) Or semi-global: block-level caused by high activity factor High temperatures raise Vt, lower Ion, raise Ioff Ion only varies ~10% between 25 and 100C Ioff can vary 5-10X This effect is deterministic in an ideal world (temp effects are in the models); in the real world, quasi-random Engineering judgement has to be used to evaluate circuits and blocks that are vulnerable to heating. Temperature effects are more important for reliability than for performance. Can have exponential impacts on Gate oxide lifetime, EM All fingers on L Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 14

15 Patterning: NOT a small challenge 65nm metal pattern Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 15

16 Lithography Process Costs Costs of Single tool increasing by ~3x every 5 years Scanner for 45nm node costs $40m Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 16

17 Lithography Costs Per Unit Area Wafer Size increases Scanner Throughput (wafers per hour) increases Net: cost per unit area declined down to 65nm node Increasing for 45 and 32nm nodes Supports relatively constant cost per chip Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 17

18 Lithography costs Per Transistor Rapidly decreasing cost per transistor fuels semiconductor device and product innovation Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 18

19 Technology Options at Technology Nodes (DRAM Half Pitch, nm) First Year of IC Production IPL, PEL, PXL nm + PSM 193 nm Strong Motivation for DFM: EUV will NOT be available 193 nm + PSM 157 nm for the next 2 technology nodes 157 nm 65 EUV, EPL ML2 IPL, PEL, PXL EUV Narrow Options WaveLength=193nm DRAM Half Pitch (Dense Lines) 45 EPL ML2 Narrow Options IPL, PEL, PXL EUV 32 EPL ML2 Narrow Options IPL, PEL, PXL EUV, EPL ML2 Narrow 22 Innovative Technology Options IPL, PEL, PXL Historical Chart (2001 A.D.) Research Required Development Underway Qualification/Pre-Production This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 19

20 A Brief (Evolutionary) History of DFM [I] Traditional Design Rules Set of geometrical constraints, necessary to guarantee yield, defined over polygonal shapes and edges in the layout The Design Rule Manual mediates among: DESIGN TECHNOLOGY FAB Two Types of DR: 1. Restrictive 2. Prescriptive 250nm, 180 nm, Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 20

21 A Brief (Evolutionary) History of DFM [II] Rule-Based Optical Proximity Correction Tables of corrections (edge movements, polygon addition and subtraction) to pre-compensate for fabrication effects and distortions, functions of (DISTANCE and SIZE) Although NOT coded in the Design Rule Manual RB-OPC is conceptually analogous to Design Rules and also implemented using same DRC engines 180 nm, 130 nm, Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 21

22 A Brief (Evolutionary) History of DFM [III] Model-Based Optical Proximity Correction (1) - Edge Fragmentation/Segmentation (2) - Iteratively: (3) Local Process Simulation (4) - Edge Movement (Correction) (5) Evaluate Edge Placement Error(s) Both Model Based And Rule-Based (geometrical) Checks 130 nm, 90 nm, 65 nm ENABLER: Layout Printability Verification Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 22

23 DFM= [DR s] + RET + (RB-OPC) + (MB-OPC) Line-End Pull-Back RET: allows for resolution, but induces proximity distortions Non-Matching Transistor Gates Necking Line-End Pull-Back Loss of Pattern Fidelity What else is needed at 32, 22 nm and below? OPC: enables RET, by restoring pattern fidelity and process window CD Control for Transistor Gates Pattern Fidelity Process/Variability-Aware Design Flows Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 23

24 Elements of DFM The Design Rules Manual at the core of DFM: Managing DR complexity Process Modeling: Geometry to Patterns to Devices to Circuits to Functions Process Variability Awareness in the Design Flow The new DFM flows: Layout Printability (Hot-Spots) Verification and Optimization Process-aware routing and synthesis Regular Fabrics/Circuits Design-Driven Metrology Top 5+1 DFM Challenges for 22nm and beyond Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 24

25 DFM Information Flows Architecture/Logic Design Circuit Design Physical Layout (GDSII/OASIS) Design Rule Verification DFM (LVS,DRC) Layout Tape-Out and Fracturing Mask Fabrication Silicon Patterning (SEM Metrology) Activation/Passivation/Intercon.,etc. Electrical Parametric Testing FAB E D A M D A Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 25

26 Inserting DFM into the design flow Process Variability Aware System Architectures IC Fab Mask Secondary DFM Insertion Primary DFM Insertion Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 26

27 Definition: DFM Design For Manufacturability (DFM): Integrated and Automated Set of Design, Simulation and Verification Methodologies 5 Objectives: i. Augment and guarantee the manufacturability of Circuit and Physical Layout Designs (Process Latitude and Yield) ii. iii. iv. Analyze the impact of CD variations and pattern fidelity on the electrical and functional performance Support/validate the selection of a Design Rules (DR) set Reduce device sensitivity to process variations v. Optimize Cost (across Design to Fabrication Flow) DFM developed as a Super-Set of DRC, RET and OPC techniques, extended to the Design and Physical Verification space Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 27

28 LOG Fixed Font-Size Design Rules Complexity Pages in a Design Rule Manual pages? 22 nm 32 nm nm pages YEAR Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 28

29 Layout dependent Yield Yield 100% Traditional Design Rule 0% 0 allowed minimum space Same Design Rule for different layout features: due to complex OPC, Optical/Process effects, etc. Feature-Feature Space Courtesy of Kevin Lucas (Freescale, Synopsys) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 29

30 Yield vs. Design Rules at 45, 32 and 22 nm DRC Clean Manufacturable Process Window Design-Rules Compliance does NOT guarantee Yield due to: Non-Linearity Effects Induced by Sub-Wavelength Fabrication. Furthermore OPC cannot fix all Yield Limiters configurations DRC Clean Process Window - Yield Limiters Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 30

31 DFM Fundamental Building Block Si-Calibrated Process Simulator To DESIGN Design Layout (GDSII/OASIS) Integrated into a verification (DRC) software environment, with a suitable programming (or scripting) language Full-Chip CD Error Map Statistical Count To FAB Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 31

32 Modeling: Levels of Abstractions Microns 1-20 Nanometers 5-15 Microns Angstroms 35,000 Microns (35 mm) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 32

33 Classes of Design Rules Corner Rounding Line-End Pull-Back Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 33

34 DFM Optimization of Design Rules [I] P1 P2 P3 P4 P5 P6 P7 Definition of Parametric Design Rule Min Max Step n P P P P P P P Total Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 34

35 DFM Optimization of Design Rules [II] Acceptable design space Simulated Parametric Space of DR+RET+OPC Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 35

36 Layout Printability Verification Process Variability Bands across Focus, Exposure, Mask Variations Process Variability Check/Flag Potential Yield Limiter Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 36

37 Printability Verification Flow SPIE 2009 Paper Jason Cain Scalability Metrics INPUT Design Layout (drawn) Silicon Target Shapes OPC Mask Shapes Process Window Simulation Measure & Characterize Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 37

38 Lithography-Driven Layout Verification and Optimization Single-Layer Multi-Layer Layout Verification and Optimization Based on Flexible Design Rules J. Yang, L. Capodieci [SPIE Microlithography, 2006: ] Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 38

39 DFM Design Analysis Application IC Design A Advanced Patterning Model Imaging Resist Etch. IC Design B CD Error IC Design B IC Design C CD Error IC Design C Full Chip Manufacturability Verification and Analysis IC Design A CD Error Design refers to Physical Layout and also Circuit Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 39

40 Design Layout Regularization ( manual ) > A nm > B nm >C nm Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 40

41 Courtesy: Lars Liebmann (IBM) Layout Re-Design Trend (65nm to 45 nm) conventional inverter 'litho'-redesign proper-redesign Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 41

42 Manual Layout Re-Design using a Layout Printability Verification Flow 32nm Metal-1 Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 42

43 Restricted Design Rules: since 65 nm Single Poly Pitch 90nm 65nm Restricted Design Rules (single pitch, single orientation) might lead to design bloat Process improved: Across Chip Line-width Variation (ACLV) in spec. How do we calculate the cost/benefit? Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 43

44 Relative Gate Count Gate Pitch Classification in Microprocessor Logic Typical Gate Occurance vs. Pitch Contacted Count Iso Min 0 Pitch category Data Source: Kevin Lucas (Motorola/Freescale) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 44

45 Regular Layouts and Piecewise Patterning Regular Layouts are needed for (enable) piecewise patterning (e.g. dual-mask) Manufacturability Constraint: Layer to Layer Alignment Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 45

46 Dual Mask Partitioning: Dipole Illumination Algorithm: Horizontal Partition Non Critical Partition Original Layout Aerial Image (Dual-Exposure) Vertical Partition H-V Partitioning steps are followed by full-chip MOPC on BOTH masks Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 46

47 Regularity in Integrated Devices Circuit Regularity Layout Regularity Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 47

48 Area (sq. microns) Regular Circuit Fabrics: Generic, Fixed-Size Configurable Bricks Firewire Area Derived Bricks Generic Bricks ASIC Number of Bricks L. Pileggi, H. Schmit, A. J. Strojwas, et al., "Exploring Regular Fabrics To Optimize The Performance-cost Trade-Off Proceedings of the ACM/IEEE DAC, June 2003 V. Kheterpal, V. Rovner, T.G. Hersan, D. Motiani, Y. Takegawa, A.J. Strojwas, L. Pileggi Design Methodology for IC Manufacturability Based on Regular Logic-Bricks Proceedings of the ACM/IEEE DAC, June 2005 Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 48

49 Advanced DFM Application: Modeling of Non-Rectangular Transistors NEW DFM FLOW: Integrated Process Simulations with Transistor Models Calibrated Process Simulation BSIM models are generated for each rectangular slice. Gate From poly line to transistor: building BSIM models for non-rectangular transistors W. Poppe, L. Capodieci [SPIE Microlithography 2006: ] Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 49

50 Si-based Timing Analysis (using Post-OPC Layout Patterns) From J. Yang, L. Capodieci, D. Sylvester SPIE-2005 Conf:5756 (Thu. 3/3/2005) Selected Speed Path Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 50

51 Si-based Timing Characterization Results (1) (2) From J. Yang, L. Capodieci, D. Sylvester SPIE-2005 Conf:5756 (Thu. 3/3/2005) Using Si-based layout reveals: (1) A re-ordering in Speed-Path criticality (2) The existence of new Speed-Paths Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 51

52 Si-based Cell Optimization for Timing From J. Yang, L. Capodieci, D. Sylvester SPIE-2005 Conf:5756 (Thu. 3/3/2005) Si-based timing analysis allows for Improved Cell Optimization (selected and ranked by slack) Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 52

53 Design Driven Metrology Design Driven Metrology (DDM) is the FUNDAMENTAL ENABLER of Design For Manufacturing (DFM) DDM establishes an operational and analytical LINK between metrology locations/results and product design components Experimental Validation of LPV Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 53

54 Design Driven Metrology Flow Design Mask SEM name row col x y loc Drawmark other meas tp_sram_m2bl_1_h NA NA 90 tp_sram_m2bl_2_h NA NA 90 tp_sram_m2bl_3_h NA NA 90 Metrology Sites Wafer Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 54

55 2D Image-Based Design Rule Checks Traditional DRC (Hard-Coded) 135 nm 405 nm nm 405 nm nm 135 nm nm nm poss_cross_spacer = EXT VIA1 == cross REGION OPPOSITE //should be a "cross" shape poss_square_spacer = EXT VIA1 == v_square REGION OPPOSITE //135 by 135nm //Verify the correctness of the "cross" spacer //Width == via_size test1 = vertex poss_cross_spacer ==12 test2 = AREA test1 == test3 = length test2!= VIA_SIZE //edges not equal via width test4 = EXPAND EDGE test3 outside by.01 cross = test2 NOT INTERACT test4 2D-DRC Image-Based Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 55

56 Layout Analysis by Pattern Matching [Data courtesy of CommandCAD] 2D (ultra-fast) Image-Based Pattern-Matching capability has been demonstrated, for full-chip layouts (X,Y) Locations of Polygonal Clips (images) can be identified Image-based pattern-matching allows for fuzzy-matching Approach can be extended to SEM images Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 56

57 2D-DR Checking (by Pattern Matching) Exact Match Fuzzy Match Full-Chip Pattern-Match (X,Y) Locations Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 57

58 Layout Analysis by Patterns Matching [II] Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 58

59 SEM Images Pattern Matching on Layouts Match Results: Exact I=226; M=89% I=84; M=94% I=226; M=89% Binary Bitmap from SEM Image Full-Chip Pattern-Match (X,Y) Locations and Fuzzy I=52; M=83% Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 59

60 DRC+: 2D DRC Verification M01 Necking DRC+ Layout Printability Verification 2 CAs printed small Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 60

61 DRC+ integration in Verification Flow From SIM to DR Integrated in CALIBRE RVE Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 61

62 R&D: Layout Pattern Clustering Clustering Analysis Printability Analysis Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 62

63 Examples of Ranked Clusters SPIE 2009 Paper Vito Dai occurences: 2 mean: occurences: 25 mean: -6.0 std. dev: 0.2 occurences: 8 mean: -4.1 std. dev: 0.5 occurences: 10 mean: -2.7 std. dev: 1.3 overall mean: -2.7 std.dev: 1.2 occurences: 1092 mean: -1.5 std. dev: 0.1 Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 63

64 Additional DFM Tasks: YRC, Density/CMP YRC (Yield Rule Checks) Identify layout geometries where recommended rules could be applied to improve manufacturability and yield. Density Analysis and CMP modeling Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 64

65 The current state of DFM DFM tools and methodologies are coming of age (at 45 nm) as evolutionary extensions of RET/OPC flows Lithography-Driven DFM, i.e. PW Layout Printability Verification, is a well established practice at 65 and 45 nm Checks/Defects CLASSIFICATION is still lacking (automation) Although many DFM Tools are available, the DFM Use-Model is still not well defined and/or well understood KEY INSERTION point for DFM is the Design Rule Manual Continuing DFM evolution drives towards more and more Regular Layouts (concept adopted also at Circuit Design Level) 2D DRC Flows have been demonstrated to identify potential Yield Detractors early in the Design-to-Fabrication Cycle Entering the age of Computational Technology Scaling Enhanced Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 65

66 Top 5+1 challenges for DFM 1. Flow interoperability and standard interfaces (models, data, XML) - requires Tool Equipment Vendors, EDA Software Vendors, FAB and DESIGN entities to collaborate [difficult] 2. Predictive modeling (ETCH, CMP, etc.) to be developed using a paradigm similar to the successful RET/OPC one (i.e. fix-it) 3. Integrated Data Mining for Process Variability Data (both simulation and experimental) directly interfaced with Design Flows 4. Process Aware Synthesis and Place & Route (not a simple problem but a fundamental enabler for 22 nm) 5. DFM Silicon Verification and predictive Yield Models (essential to quantify ROI in DFM) Require also substantial advances in Metrology Automation (CAD) Process-Variability-Aware System Architectures design time run time Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 66

67 Acknowledgments Rich Klein, Norma Rodriguez, Marilyn Wright, Rolf Seltmann, Cyrus Tabery, Sarah McGowan, Carl Babcock, Chris Spence, Yi Zou, Jie Yang, Vito Dai, Ethan Cohen, Uwe Hahn, Mark Craig, JR Zhou, Ed Roseboom, Stefan Roling, FAB1/A/B, Norman Chen, Chidam Kallingal, Jason Cain, and many, many others at AMD and GLOBALFOUNDRIES Luigi Capodieci, Ph.D. - R&D Fellow - GLOBALFOUNDRIES Managed Variability and DFM 67