Introduction to Digital VLSI Design מבוא לתכנון VLSI ספרתי
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1 Design מבוא לתכנון VLSI ספרתי Extraction Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel Slide 1
2 Extraction Extraction is a process of creating electrical representation (R&C) for layout interconnect Extraction could be done in two ways: 1. transistor level extraction 2. cell level extraction Resistance & Capacitance Slide 2
3 Delay calculation Total delay = device delay + interconnect delay + slew rate Slide 3
4 Basic concepts Capacitance Area (overlap) Fringe (edge) Nearbody (coupling) Slide 4
5 Parasitic Extraction What is parasitic capacitance? Electrical side effect depends on the shape of the signal and its neighborhood. Parasitic capacitance occurs both between geometries on a single layer and between geometries on different layers. Slide 5
6 What is parasitic resistance? Electrical side effect depend on the shape of the signal and resistivity of the interconnect layer Slide 6
7 Grounding coupling capacitors 20 pf 20 pf 20 pf RC representation: 1. C (lumped C) 2. RC (distributed RC) 3. RCC (distributed RC + coupling) Slide 7
8 Layout formats GDSII (stream) raw geometrical shapes LEF / DEF geometric shapes + netlist Slide 8
9 GDSII format Raw geometric shapes (polygons, paths) at diffrenet layers Texts (net names, pin names) at different layers Cell instances Available: Always Connectivity: Requires connectivity analysis and LVS Slide 9
10 LEF (abstract) Cell boundary Cell pins with names and locations Obstructions (used routing area) Slide 10
11 DEF Represents one level of layout Netlist, pins locations, cells placement, routing annotated per net Connectivity All the information embedded inside the LEF/DEF; no need for special processing Available from automatic P&R tools Slide 11
12 RC Formats DSPF (= SPF) most often used SPEF SPICE SBPF (for PrimeTime only) Slide 12
13 DSPF resistance and line capacitance of each segment in a net in a SPICE format Non SPICE statements: * NET NetName NetCap * I (InstancePinName InstanceName PinName PinType PinCap X Y) * P (PinName PinType PinCap X Y) * S (SubNodeName X Y) Slide 13
14 Net name and total capacitance Net nodes Port node Instance pin Subnode Capacitors Resistors * NET cpm_ips_rdata[2] PF * P (cpm_ips_rdata[2] O ) * I (sba_env:cpm_ips_rdata[2] sba_env cpm_ips_rdata[2] B ) * I (sbs_env/sbs_top:sbs_ips_rdata[2] *+ sbs_env/sbs_top sbs_ips_rdata[2] B ) * S (cpm_ips_rdata[2]:9) Cg1540 sba_env:cpm_ips_rdata[2] e-14 Cg1541 cpm_ips_rdata[2] e-14 Cg1542 cpm_ips_rdata[2]: e-14 Cg1543 sbs_env/sbs_top:sbs_ips_rdata[2] e-14 R1189 cpm_ips_rdata[2]:9 sbs_env/sbs_top:sbs_ips_rdata[2] 30.2 R1190 sba_env:cpm_ips_rdata[2] cpm_ips_rdata[2]: R1191 cpm_ips_rdata[2] cpm_ips_rdata[2]: cpm_ips_rdata[2] sba_env:cpm_ips_rdata[2] sbs_env/sbs_top:sbs_ips_rdata[2] Slide 14
15 Extraction tools xcalibre (GDSII) Calibre2Star (GDSII) StarXT (LEF / DEF) Slide 15
16 Target tools Timing Analysis tools (Cell and Trasistor Level) Noise Power grid Circuit Verification Tools Slide 16
17 The Flows Cell Level Transistor level extraction on GDSII LVS required Usually extract capacitance only Used for characterization, or in transistor level analysis tool with cell level block extraction Slide 17
18 The Flows Block Level Transistor Transistor level Transistor level level Cell level Slide 18
19 Chip level extraction on LEF/DEF down to block boundaries no LVS required extract RC extraction tool - StarXt analysis tool - PrimeTime backannotation - no need reduction - done on-the-fly need to define context to model inside blocks routing if obstructions do not exist Slide 19
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