LC VCO Design Procedure

Transcription

1 L VO Design Procedure 116

2 UMTS VO VO design parameters Design requirement Oscillating frequency 2.1GHz Tuning range 400MHz Voltage swing 0.7V Phase noise Supply voltage 3V Power consumption 10mW Technology parameters Values Technology BiMOS Number of metals 4 Transit frequency 50GHz MIM capacitors available Varactors available WDMA Specs Value Receiving Band (GHz) hannel Spacing (MHz) 5 (3.84) Multiplex / Modulation FDD / QPSK MDSeff (dbm) -99 SNR (db) / BER 7 / 1E-3 Processing Gain (db) 25 Tx-Rx Isolation (db) 50 8MHz (db) -46 L (8MHz)=-99-(-46)-10log(3.84e6)-7=-129dBc/Hz 117

3 Series vs. Parallel Resonator frequency f 0 =2.1GHz desired signal power P=10mW R S L Q L =20 R TK L L=3nH, =1.9pF, R S =2Ω fundamental current and voltage i=100ma, v=0.2v L=3nH, =1.9pF, R TK =800Ω fundamental current and voltage i=5ma, v=4v very large current moderate current and voltage realistic choice 118

4 Negative Resistance Oscillator V L, V U T RL V 1 ω 0 = L = V / 2 resonating L tank g m / 2 active part Q 1 Q 2 I TAIL I = I T 2 biasing current source Q S Q S 119

5 L Tank Design oscillation frequency f 0 = 1 2π L = V / 2 determine L and tuning range f f MAX MIN = V,MAX + 2 V,MIN PAR 1+ 2 V,MIN PAR V,MIN parasitics impose larger capacitive tuning range V,MAX V,MIN f MAX MAX = 2 1 f MIN 2 + f f MIN 2 PAR V,MIN determine MAX and MIN 120

6 How to hoose L? tank conductance G TK = ω L Q choice of L L + 1 Q L( phase noise Δω ) KT R L + 2R V 2 S F ω 0 Δω 2 larger L => larger Q L larger L => lower G TK larger L => lower power consumption larger L => larger R L larger L => poorer larger L => lower f RES, f Q-PEAK larger L => lower tuning range L choose for the largest L having peak Q close to the operating frequency 121

7 How to hoose? tank conductance phase noise G TK RL = ( ω L ) choice of R ( ω ) larger => lower Q larger => larger G TK 0 2 Δω larger => larger power consumption larger => larger tuning range L( ) KT R L + 2R V 2 S ω 0 F Δω larger => lower R larger => slightly better L 2 choose for providing not more than the required frequency tuning range 122

8 Active Part Design chosen L tank parameters determine losses to be compensated G TK RL = ( ω L ) g M = g m 0 / R ( ω ) cross-coupled pair conductance 0 2 oscillation condition g M >G TK determines the very minimum compensating active-devices current R L 2 I = g mvt > 2GTKVT = 2 + 2R ( ω ) VT ( L ) 2 0 ω 0 choose for the transistors having enough f T (~10f 0 ) for the determined collector current 123

9 What About Phase Noise? there is nothing better than the best L-tank the best L tank chosen determines power consumption and accordingly active devices operating current shot noise is directly determined by operating current, i.e., L tank the larger the transistor the lower the base resistance thermal noise (but more parasitics) choose for as large transistors as possible having enough f T (~10f 0 ) for the determined collector current 124

10 Tail urrent Source Tail current noise around even multiples of the oscillating frequency is transformed into the phase noise of the VO Tail current noise contribution larger than all other contributions together Reducing the output noise power of the current source, its contribution to the phase noise is reduced as well emitter degeneration reduces the tailcurrent source noise transfer functions resistive degeneration effective at all frequencies but requires voltage headroom inductive degeneration effective in narrow frequency band but requires no voltage headroom V B,S Q S I B,S I S, RID Z D I,S 125

11 So Far VO design parameters Design requirement Oscillating frequency 2.1GHz Tuning range 400MHz Voltage swing 0.7V Phase noise Supply voltage 3V Power consumption 10mW Technology parameters Values Technology BiMOS Number of metals 4 Transit frequency 50GHz MIM capacitors available Varactors available 126

12 Simulations/ Layout/ Measurements 127

13 Design Procedure alculations estimation of design parameters Simulations Layout Measurements 128

14 Simulations Simulation with estimated idealized components adjustment of estimated design parameters Simulation with components models provided by technology adjustment of estimated design parameters 129

15 Layout Layout design Layout extraction Postlayout simulation adjustment of circuit and layout parameters Layout verification design rules check layout versus schematic check 130

16 Measurements (Design Verification) hip packaging Printed ircuit Board design Measurement setup Simulation of measurement setup I-package-PB Interpretation of measured results 131

17 VO Design Example - Simulations 132

18 Idealized VO Schematic V V L V L=3nH, Q L =25, V0 =3.8pF U T A =150fF, B =600fF B B Q 1 Q 2 collector current (0.2mA, 3mA) A R B R B A transistor dimensions 0.5x10um 2 V B I TAIL tail current (0.4mA, 6mA) Q S Q S TS transistor dimensions 0.5x20um 2 L RID =3.4nH L RID L RID 133

19 VO Schematic with Inductor Model L L/2 /2 R L V R L /2 L L/2 OX SUB R SUB V SUB OX R SUB R U R T V L=3nH n=3, w=20um d OUT =320um, s=5um B B Q 1 Q 2 A R B R B A V B LRID=3.4nH I TAIL n=6, w=7um Q S Q S d OUT =120um, s=1um L RID L RID 134

20 VO Design Example - Layout 135

21 Layouting omponents placement and routing hip padding Isolation guard rings Protection Electrostatic Discharge (ESD) Substrate contacts, metal distribution 136

22 VO Layout Top View bond pad L RID L RID -g M L 137

23 Placement Generation of component layouts omponent Separation sensitive I/O nodes (RF/LO) sensitive circuits (power amplifiers/oscillator) sensitive sub-systems (analog/digital) omponent coupling substrate, interconnects, bondwires 139

24 Routing Track width/length thick(wide)/long/top thin(narrow)/short/bottom urrent density wide ground/supply lines Bottom metal component interconnect Top metal circuit/system interconnect 140

25 Padding I interface inputs/outputs information signal lines bias lines supply, ground Area increase size 100x100um 2 distance 100um ESD for sensitive nodes HF circuit performance degradation capacitance added 141

26 Design Rules (Layout Verification) omponent size (width/length) omponent spacing Track width Track spacing Metal density Geometry Grid 142

27 Design Rule ompliant VO Layout Design Rule heck (DR) omparison of layout and schematic (LVS) Generation of output file for fabrication (GDSII) 143

28 VO Design Example - Measurements 144

29 hip and Measurement Equipment - Interface 145

30 Verification Procedure Oscillator chip packaging Oscillator I Printed ircuit Board design Measurement setup Interpretation of the results 146

31 VO hip Microphotograph L RID L RID -g M L 147

32 Packaged VO I VO chip bondwire bondpad 149

33 Packaged VO I on PB SMD transformer SMD resistor VO I package SMD inductor SMD capacitor bias choke 150

34 Measurement Fixture I/O connectors transformer bias filtering VO I bias filtering package PB 151

35 Package and PB Effects Measured vs. simulated Include into simulations bondwire inductance package lead inductance contact capacitances SMD components on PB transmission lines on PB topb L PKG L BW tovo PB PKG BPAD 152

36 Measurement System V + V VO + V -XF + + U TUNE Spectrum analyzer LO test fixture + I BUFFER V VO I TAIL V I BUFFER 153

37 Measured Signal Spectrum signal power signal frequency 154

38 Measured Frequency Tuning Range f LOW =1.8GHz f UP =2.4GHz 2,5 2,4 Δf=600MHz Oscillating frequency [GHz] 2,3 2,2 2,1 2 1,9 V =3V V TUNE =3V 1,8 1,7 0 0,5 1 1,5 2 2,5 3 Tuning voltage V T [V] 155

39 Measured Phase Noise 156

40 Measured VO Performance VO design parameters Measurement Results entral frequency 2.1GHz Tuning range 600MHz Voltage swing 0.7V Phase noise Supply voltage 3V Power consumption 3mW 157

41 onclusions 159

42 So far Oscillator classification Oscillation condition frequency, amplitude Oscillator phase noise UMTS oscillator design estimation, simulation, layout, measurements 160

43 Job Offer RF/analog circuits design experience oscillators AD design adence, ADS Measurements and PB design Salary