Hypersensitive parameter-identifying ring oscillators for lithography process monitoring

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1 Hypersensitive parameter-identifying ring oscillators for lithography process monitoring Lynn Tao-Ning Wang* a, Wojtek J. Poppe a, Liang-Teck Pang, a, Andrew R. Neureuther, a, Elad Alon, a, Borivoje Nikolic a a Dept. of Electrical Engineering and Computer Sciences, Univ. of California/Berkeley, Berkeley, CA USA *Ting0918@eecs.berkeley.edu ABSTRACT This paper applies process and circuit simulation to examine plausible explanations for measured differences in ring oscillator frequencies and to develop layout and electronic circuit concepts that have increased sensitivity to lithographic parameters. Existing 90nm ring oscillator test chip measurements are leveraged, and the performance of ring oscillator circuit is simulated across the process parameter variation space using HSPICE and the Parametric Yield Simulator in the Collaborative Platform for DfM. These simulation results are then correlated with measured ring oscillator frequencies to directly extract the variation in the underlying parameter. Hypersensitive gate layouts are created by combining the physical principles in which the effects of illumination, focus, and pattern geometry interact. Using these principles and parametric yield simulations, structures that magnify the focus effects have been found. For example, by using 90 O phase shift probe, parameter-specific layout monitors are shown to be five times more sensitive to focus than that of an isolated line. On the design side, NMOS or PMOS-specific electrical circuits are designed, implemented, and simulated in HSPICE. Keywords: ring oscillator, lithography, layout, focus monitor, phase-shifting mask, electronic testing, variability, DfM 1. INTRODUCTION Ring oscillator frequency data is an effective method for assessing manufacturing performance variation. While acquiring the data requires chip fabrication, it is possible to electrically measure quickly and produce a large body of information on performance variation versus location within the die, within the field, across the wafer, wafer to wafer, and lot to lot. Once the data is taken, however, it is very difficult to explain the sources of ring oscillator variation. This is because the ring oscillator, like the circuit itself, is dependent on many manufacturing factors. Ring oscillators have been reported as being very effective for monitoring production and identifying across chip variations for the same layout [4]. An example of extensive ring oscillator measurements, available to the authors, is the use of various gate geometry layouts as conducted by Liang-Teck Pang and Borivoje Nikolic at the Berkeley Wireless Research Center (BWRC) in collaboration with STMicroelectronic [1]. An approach to help unravel ring oscillator dependence in an automated manner is the Collaborative Platform for DfM developed by Wojtek Poppe [2]. This system combines lithography, non-planar transistor modeling, and circuit simulation. This paper uses the collaborative platform for DfM with generic process models to study CMOS ring oscillator circuits for the identification and quantification of sources of variability. Specifically, the paper explores three key uses. After background on the measurement and modeling techniques in Section 2, the platform is used in Section 3 to compare with the kinds of trends in variability seen in the experimental characterization of Pang. In Section 4 the platform is used to screen existing test structure layouts for improved sensitivity and to explore new phase-shifting layouts that are hypersensitive to focus. Finally, in Section 5, concept for improving the specificity of a circuit to NMOS versus PMOS effects is described. 2. BACKGROUND ON MEASUREMENTS AND MODELING 2.1 Example Results from 90nm Test Chip Design for Manufacturability through Design-Process Integration II, edited by Vivek K. Singh, Michael L. Rieger, Proc. of SPIE Vol. 6925, 69250P, (2008) X/08/$18 doi: / Proc. of SPIE Vol P-1

2 36 chips, 4032 data fastest coupt simulation slowest gffl RO frequency (F) Mizizi lilolol 1hz zi LIz 01 izizi IZIZI Tile 3a Tile 4a Tile 5a Figure 1. Example Results from 90nm Test Chip Figure 1 presents example results from the 90nm test chip developed by Pang [1]. For each across-wafer distribution, the fastest and the slowest chip for a 1mm by 1mm die are shown. From the measured data, a within die 3σ/µ variation of 3% is observed, and an across-wafer 3σ/µ variation of 18-20% is observed. Another interesting case is when one of the dummy polys is removed, a maximum frequency increase of 10% is observed (shown in Tile 4a and Tile 5a measured data). However, whether the dummy poly is placed to the right or left of the gate-under-test has minimal effect on the ring oscillator frequency the measured difference is approximately 1%. The measured data could be explained using simulations in HSPICE and the Collaborative Platform for DfM [2]. 2.2 Parasitic Capacitance and Frequency Sensitivity Study The basis ring oscillator performance is sensitive to geometry variations of both the NMOS and PMOS gates. Figure 2 presents a capacitance and a comparative frequency sensitivity study of the normalized ring oscillator performance to the normalized fractional change in the NMOS gates, PMOS gates, and both the NMOS and PMOS gates. Normalized RO Freq vs. Normalized Channel Length Normalized RO Frquency Slope = Tile 3a Both Tile 4a Both Tile 5a Both Tile 3a NMOS Tiela 3a PMOS Slope: Normalized Channel Length Figure 2. Drawn Layout Capacitance and Frequency Sensitivity Study Proc. of SPIE Vol P-2

3 Without any lithography simulations, the drawn gate channel length for NMOS, PMOS, and both NMOS and PMOS is varied for layouts Tile 3a, Tile 4a, and Tile 5a. The change in ring oscillator frequency due to the varying of the drawn channel length is simulated via HSPICE, and results are presented in Figure 2. The frequency increase seen in the measured data for Tile 4a and Tile 5a compared to that of Tile 3a is not due to parasitic capacitances since the three sensitivity curves for each of the layouts collapse on to one another. Also, a change in 10% drawn channel length causes an 18.1% change in ring oscillator frequency. This could be observed from the slope at (1.00, 1.00), where slope is defined as the ratio of change of the normalized ring oscillator frequency to the normalized drawn channel length. Figure 2 shows that the combined effect of varying both NMOS and PMOS is twice as sensitive as that of varying NMOS or PMOS alone. For the NMOS or PMOS gates alone, the sensitivity to gate length change is When both the NMOS and PMOS gates change together by the same fraction, the sensitivity is 1.81 The reason behind the comparative analysis shown in Figure 2 is due to the fact that the Collaborative Platform for DfM consists only of the NMOS non-rectangular transistor model. 2.3 Collaborative Platform for DfM: Parametric Yield Simulator (PYS) Calibre Module 1 Processing Module 3 Circuit Circuit Simulation across characterized process window BSIM transistor model Module 2 Device Non-rectangular transistors Figure 3. Parametric Yield Simulator (PYS) The study conducted here is based on the actual layouts developed by Pang for the 90nm ST Microelectronic technology as inputs to the Parametric Yield Simulator (PYS) in the Collaborative Platform for DfM. Figure 3 presents the flow of PYS. Layouts input in to Calibre. A lithography simulation is then made of the layouts to predict gate contour shapes. For the NMOS devices, the gate shapes are then converted using a non-rectangular transistor model to an equivalent rectangular gate length for a generic BSIM model available at [5]. The HSPICE parameters are then extracted for the original layout. The process modeling shown is generic and without calibration against actual silicon. Specifically for the 193 nm dry lithography, a numerical aperture of 0.78 and annular illumination with sigmas of 0.88 and 0.4 are assumed. A predictive 90nm BSIM model that can be obtained from [5] is used. The focus ranges to plus and minus 0.75 Rayleigh units. The dose is varied from plus to minus 6% from nominal. A variable threshold resist is used for a typical resist. From Parametric Yield Simulations, Bossung plots of the variation in effective non-rectangular linewidth (Leffective) versus focus and dose is shown in Figure 4 and Figure 5. The data has the basic Bossung shape although the nominal dose might have been increased by a few percent centered on a less focus dependent linewidth. Both isolated line (Figure 4) and dense lines (Figure 5) are shown for comparison. Proc. of SPIE Vol P-3

4 For purposes of sensitivity analyses, observations from the range of -80nm to 40nm focus are quoted. This corresponds to a 120 nm range from edge to center of focus, approximately 0.75 of a Rayleigh unit. Percent variation in Leffective is extracted from the curvature under nominal dose condition. L effective. vs. Focus: 90nm 110 Leffective (nm) Defocus (nm) Figure 4. Bossung Plot of Leffective vs. Focus and Dose for 90nm Isolated Line L effective. vs. Focus: Tile 3a 110 Leffective (nm) Defocus (nm) Figure 5. Bossung Plot of Leffective vs. Focus and Dose for Dense Layout From the sensitivity range of -80nm to 40nm focus, for the isolated line layout (Figure 4), a 5.5% variation in Leffective is noted. For the same range, a 3.0% variation in Leffective is observed from the dense layout (Figure 5). 3. PREDICTION OF RING OSCILLATOR FREQUENCY VARIATION The prediction of electrical ring oscillator frequency is based on the lithography modeling, non-rectangular extraction, and circuit analysis. Figure 6, 7, and 8 are obtained by extracting the Leffective of the NMOS transistor from Parametric Yield Simulations and simulating the original ring oscillator with the extracted Leffective via HSPICE. These results do not include any changes in the CMOS devices and so should predict only about half of the variation observed Proc. of SPIE Vol P-4

5 experimentally. Figure 6 shows a Bossung-type plot for ring oscillator performance for dense layout structure (Tile 3a) versus focus and dose. RO Freq. vs. Focus: Tile 3a 1.12 Normalized RO Freq Defocus(nm) Figure 6. Bossung Plot of Ring Oscillator Frequency versus Focus and Dose Recall from Figure 1 that the across-wafer 3σ/µ variation is approximately 18-20%. Assuming a process window of + 2% dose and -80nm to 40nm focus (denoted by the circles in Figure 6), we observe only a 5.2% variation in frequency, instead of the 18-20% measured variation. This implies that the frequency variation is due to a non-lithographic cause. 3.1 Study of Layout Asymmetry Prediction of ring oscillation frequency for layout Tile 4a and Tile 5a is shown in Figure 7. RO Freq. vs Focus: Tile 4a & 5a 1.2 Normalized RO Frequency a_94 5a_ 5a_106 4a_94 4a_ 4a_ Defocus (nm) Figure 7. Ring Oscillator Frequency vs. Focus for Different Dose Conditions for Tile 4a and 5a Figure 7 presents Bossung plots for both Tile 4a and 5a for ring oscillator frequency versus focus and dose. The two sets of curves are very similar, which show that the split between the two layouts due to the effect of symmetry on Leffective is well less than 1 nm and hence below 1%. This small split agrees with there being a negligible difference in measurements from Tile 4a and 5a. Since the curves are identical to within 1% of Leffective for Tile 3a, coma does not Proc. of SPIE Vol P-5

6 appear to account for the shift of Tile 4a and 5a to higher frequencies. Etching of a gate with a dummy poly on only one side would however be consistent with a frequency increase. 4. IMPROVED LAYOUT MONITORS Layouts with very high sensitivities to exposure, focus, and lens aberrations can be used as monitors for sources of variation. Isolated lines are such a feature, being highly sensitive to focus, and will serve as the reference point for even more sensitive layouts. The design and analysis of improved focus monitors are explored in this section. Layout sensitivities may be evaluated using the Collaborative Platform for DfM to identify good candidates. An initial screening study using the Collaborative Platform was conducted by Wojtek Poppe for multi-fingered gates [8]. Figure 8 shows the evaluation of this layout for sensitivity to focus. A high sensitivity to focus for gate spacings prior to SRAF insertion is observed. CD shift with Defocus (OPC) CD shift from nominal (nm) 4 20nm nm 3 60nm 80nm Focus Sensitive Pitch Focus Insensitive Pitch -1 pitch (nm) Figure 8. Through pitch response to focus of the center line in a five, 80nm line arrays. Figure 8 shows the CD shift versus pitch, where CD shift is the difference between the simulated dimension at nominal conditions and at the specified level of defocus. The encircled region shows a 4.5% shift from nominal CD. L effective. vs. Focus: Non-Rectangular Geometry Leffective (nm) DOF(nm) Defocus (nm) (a) Figure 9. Parameter-Specific Layout Monitor: Gate with a Bulge in the Center An even more sensitive layout monitor, shown in Figure 9(a), consists of a gate with a bulge in its center. Figure 9(b) shows the Bossung plots of Leffective versus focus and dose for the focus monitor. For the same sensitivity region of - (b) Proc. of SPIE Vol P-6

7 80nm to 40nm of focus, a 12.8% variation in Leffective is observed. This is twice as sensitive as the point of reference, the isolated line shown in Figure 4. L effective. vs. Focus: 1-Ring Defocus Target Leffective (nm) Defocus DOF(nm) (nm) (a) (b) Figure 10. Parameter-Specific Layout Monitor: Interferometric 90 O Phase Shift Juliet Rubinstein and Wojtek Poppe also developed layouts for gates with additional surrounding features that were substantially more sensitive to focus than the isolated line shown in Figure 4 [6][7][8]. The most sensitive of these designs utilize regions with a 90 O probe and could detect the sign as well as magnitude of defocus. An example of such a monitor is shown in Figure 10(a). The focus monitor consists of a gate with the source to the left and drain to the right of the gate. The box in Figure 10(a) represents a 90 O probe on top of the gate. The amount of light spillover into the central probe depends on the direction of focus. The Bossung plot for this monitor is shown in Figure 10(b), showing Leffective versus focus and dose. The linear relationship across focus in Figure 10(b) makes this design particularly useful as a monitor. For the sensitivity range of - 80nm to 40nm of focus, a 27.8% variation of Leffective is observed. This monitor is five times more sensitive than that of the point of reference, the isolated line, and is thus termed as a hypersensitive layout monitor. Table 1 presents a summary of Leffective variations presented in this paper. Focus Monitors -80nm to 40nm Focus Dense 3.0% Isolated 5.5% Bulge (nonrectangular) 12.8% Phase Shift 27.8% Table 1. Summary of variation in Leffective from -80nm to 40nm Focus 5. IMPROVED ELECTRICAL CIRCUITS A great area for invention is combining circuit knowledge with device sensitivity to manufacturing parameters in order to identify and quantify variations. Ripe areas include creating and operating circuits in modes that are highly sensitive to any change. They also include developing device and parameter isolation schemes. An example here is a new circuit Proc. of SPIE Vol P-7

8 design for which the performance is dominated by NMOS or PMOS only and thus facilitates characterization of these devices individually. Large P-MOS to enable fast pull-up Vfb Vin Vout Gate under Test 10x inverter with small lithography effects Connects back to Vfb to reset earlier stages Figure 11. Basic Module: NMOS-Sensitive Electrical Circuit Shown in Figure 11 is an NMOS-sensitive self-reset circuit that has been designed, implemented, and simulated in HSPICE. It consists of an NMOS gate under test, a large PMOS for fast pull-up, and a large inverter that is sized ten times bigger than the rest of the circuit so that it would less vulnerable to lithography variations. The feedback node connects back to the large PMOS to rest the earlier stages. I Control Module Module Module Module Module Module Input Buffer Scan Chain Enable/Disable Feedback/Reset Network Figure 12. Six-Stage Self-rest Circuit Figure 12 shows a six stage self-reset circuit that is implemented in HSPICE. It consists of a control network with a sixstage module. There is a signal feedback every three modules to reset earlier signals. Proc. of SPIE Vol P-8

9 H : _±.-- ±_-_._±._. ±_-.!!. ±_ Figure 13. Simulations Results for Self-reset Circuit Show Sensitivity to N-MOS Devices Figure 13 shows simulation results for the NMOS-sensitive self-reset circuit. If the drawn gate length is varied by 10% in the NMOS device under test, the output frequency changes by 8%. By comparison, if the drawn gate length of the PMOS device were varied by 10%, the ring oscillator frequency changes by only 2%. This circuit is 4 times more sensitive to the NMOS than to the PMOS. This circuit could be made even more sensitive by increasing the PMOS/NMOS transistor ratio. 6. CONCLUSIONS Possible ring oscillator variations are examined by looking at the existing ring oscillator measurements for the 90nm test chip developed by Liang-Teck Pang and by looking at the corresponding simulations using the Collaborative Platform for DfM by Wojtek Poppe that allows processing, device modeling, and circuit performance to be analyzed. Variations seen in measured data is concluded not to be dominated by lithography. While the measured data from the 90nm test chip show a 3σ/µ across wafer variation of 18-20%, simulations show that lithography is well-controlled, and only 5.2% variation across an assumed process window is attributed to lithography. Hypersensitive 90 O phase-shift layout monitors with five times the sensitivity to focus compared to that of an isolated line are recommended. Lastly, novel circuit concepts can improve NMOS and PMOS device specificity. A circuit that shows an NMOS sensitivity that is 4 times greater than that of the PMOS is presented. 7. ACKNOWLEDGEMENTS The authors would like to acknowledge STMicroelectronic for chip donation, Mentor Graphics for Calibre tool donation, the industry through the UC Discovery Program and SRC 1443, and FLCC/IMPACT grant: Advanced Micro Devices, Applied Materials, ASML, Cadence, Canon, Cymer, Ebara, Hitachi Global Storage Technologies, Intel, KLA-Tencor, Magma Mobility Electronics, Mentor Graphics, Nikon Research, Novellus Systems, Panoramic Technologies, Photronics, Synopsis, Tokyo Electron, Toppan Photomasks, IBM, Xilinx, Marvell, and Sandisk. 1 REFERENCES L.-T. Pang, B. Nikolic, Impact of Layout on 90nm CMOS Process Parameter Fluctuations, 2006 Symposium on VLSI Circuits, Digest of Technical Papers. N. Bluzer and A. S. Jensen, "Current readout of infrared detectors," Opt. Eng. 26(3), (1987). 2 A.H. Gabor, et al, Improving the Power-Performance of Multicore Processors Through Optimization of Lithography and Thermal Processing, SPIE, Volume (2007). Proc. of SPIE Vol P-9

10 3 W. Poppe, et al, Platform for collaborative DFM, SPIE, Volume 6156 (2006). 4 Y. Borodovsky, Impact of Local Partial Coherence Variations on Exposure Tool Performance, SPIE, Volume 2440 (1995) J. Rubinstein, A. Neureuther, Images in Photoresist for self-interferometric electrical image monitors, Proceedings of the SPIE, Volume 6730, pp (2007) 7 J. Rubinstein (Holwill), and A. Neureuther, Self-Interferometric Electrical Image Monitors, SPIE Microlithography - Design and Process Integration, February, W, Poppe, Ph.D Thesis, December 2007 Proc. of SPIE Vol P-10