Yield-driven Robust Iterative Circuit Optimization

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1 Yield-driven Robust Iterative Circuit Optimization Yan Li, Vladimir Stojanovic July 29, 2009 Integrated System Group Massachusetts Institute of Technology

2 Systems-on-chip is difficult to design Integrated radio transceiver [Infineon] Integrated high-speed memory and logic interfaces [IBM CELL Processor] Both links and radios are now highly integrated Overall yield limited by each block

3 Complex design blocks Wireless transceiver High-speed transceiver SysClk TX Data Parallel to Serial TX EQ Tclk Vtt TXP TXN TX RefClk 1/4 or 1/5 1 or 1/2 PLL Phase Mixer Phase Mixer Mixer Rclk Cloc Phase Control Vtt RX Data RX Clk Serial to Parallel Rclk RXP RXN RX RX Equalizer Tap Selection Tap Weights Embedded mixed-signal design for each block

4 Target design blocks LNAs PLLs ADCs Link samplers inp inn I Ithresh 2 outn outp inp I Ithresh 2 clk outp clk clk outn Q Q TIAs pre-amp with offset comparator

5 Target design blocks LNAs PLLs ADCs We start from amplifiers Link samplers inp inn I Ithresh 2 outn outp inp I Ithresh 2 clk outp clk clk outn Q Q TIAs pre-amp with offset comparator

6 Challenge from process variations Year DRAM pitch(nm) Total gate 3 (nm) LER 3 (nm) ITRS Manufacturable solutions are known Manufacturable solutions are NOT known Variations challenge the analog/mixed-signal circuit design V th variation doubled for each technology node < 100 nm Designers take care of the problem Smart compensation techniques Resizing circuits smartly???

7 Current design flow Designers traditional robust design flow Iterations provide poor feedback to designers Time consuming

8 Improve the design flow with optimization Methodology for yield-aware large scale mixed-signal/rf circuits design Limitations of state-of-art design methodologies Proposed algorithm on a two-stage Op-amp example Results & Conclusions

9 Equation-based optimization flow Equation-based optimization: fast global design space search Problems Robust optimization intractable Hard to link process variation distribution to performance distribution & yield

10 Limitations of robust circuit optimization Direct solving with approximations Solving robust GP problem Boyd Piecewise-linear convex approximation Circuits are strictly GP compliant Iterative solving method Worst-case distance -- Antreich Simulation-based Bounded variation Mutapcic Different worst-case search technique Needs a careful adaptation to circuit optimization

11 Proposed robust optimization flow Key insight: Reduce the challenge in robust optimization by simplifying variability model bounded variations (Mutapcic) Iterate to improve the yield (mimic the traditional design flow)

12 Intuitions behind the algorithm

13 Algorithm details for an op-amp example Need to adapt to circuit optimization with consideration of circuit specific issues Example Variations: V th and (current factor) for all 8 transistors Design variables: transistor sizes, biasing conditions Constraints: specs on gain, bandwidth, phase margin, slewrate & CMRR + biasing constraints Objective: minimize weighted area and power

14 Step 1: Worst-case (W.C.) analysis Start from a design without consideration of variations

15 W.C. with constraint maximization maximize 1/BW X * =(W *,L *,Iref * ) maximize 1/Slew rate M20 M14 Vdd M22 Transistor macro model M20 M14 Vdd M22 Transistor macro model Iref M11 ip M12 in Cc out - + Iref M11 ip M12 in Cc out - + M9 M10 M21 V T M9 M10 M21 V T Sign( V * T) Sign( V * T) Maximization done on each performance constraint separately Variables: ΔV T Constraints: biasing + bounds Record the sign of each V T Use transistor macro-model to satisfy KCL, KVL biasing for different variability

16 Worst-case corner from GP-based solver Question in maximization with V T variation Don t know the sign of V T the GP-based solver only handles positive variables Circuit constraints often monotonic locally in variability Easy to find a solution in the positive region Find direction in positive region and map to full space

17 Step 2: Robustified optimization (R.O.)

18 R.O. via multi-scenario robustified optimization Sign( V * T ) Sign( V * T) Robustification Share the same design variables X (W, L, Iref) M20 Iref M11 ip M14 Vdd Clone 1 Clone 2 M22 M12 in out Transistor macro model M20 Iref M11 ip M14 Vdd M22 M12 in out Transistor macro model Nominal Vdd M20 M14 M22 Iref M11 M12 ip in out Cc M9 M10 M Sign( V T ) Cc M9 M10 M Sign( ) V T Cc M9 M10 M21 New design X* Clone circuit to represent worst-case scenario for each performance constraint Same topology with macro transistor model Polarity of the V T determined from constraint maximization Multi-scenario optimization leads to a new design

19 Algorithm putting everything together

20 area (m 2 ) power consumption (mw) gain yield (%) Results--Two-stage Op-amp 1 corner Optimization and simulation results give the same trend on yield Tradeoffs between performances and power/area opt 20 sim iterations iterations 6 7 yield (%) opt 20 sim iterations iterations

21 Area (m 2 ) Power (mw) Power (mw) DC gain yield (%) Bandwidth yield (%) Bandwidth yield (%) Results--Two-stage op-amp 5 corner 5-corner initial design SS corner results opt opt sim sim iterations Iterations iterations iterations 4 5 # corner Temp (K) Vdd (V) Iref (ua) 1 tt ss ff fs sf opt opt 20 sim 20 sim iterations Iterations corner 1 corner 2 corner 3 corner 4 corner 5

22 Results folded-cascode example Problem setup: 90nm predictive model 32 V th variations Specs: Gm [0.5mS, 0.6mS], gain>50 db, phase margin> 60, CMFB gain>60 db, CMFBωμ>5.9MHz

23 # of samples # of samples Results robust design results Monte-carlo simulations for design before and after robustifying iter Violated constraints Gm (ms) Yield (%) Area (um^2) Power (mw) 0 Gm > Gm< None None Fail Initial design Pass Pass 4 None Fail Gm (ms) 60 Final robust design Gm (ms)

24 Results Problem size Problem size in each step of one iteration Iteration breakdown Two-stage op-amp Folded-cascode op-amp # var # constr # var # constr Nominal design Maximization Redesign with 1-scenario Redesign with 2-scenario Problem size linear in number of performance specifications

25 Results computational cost Time measured in a Linux server with 3.16GHz Intel Xeon processor and 16 GB memory min to get a robust design with yield > 90% Iteration breakdown Two-stage op-amp Folded-cascode op-amp Nominal design 10 s 17 s Redesign with 1-scenario 11 s 30 s Redesign with 2-scenario 20 s 40 s Maximization 6 specs: 20s 5 specs: 1min

26 Conclusion Traditional circuit design with variability lacks sensitivity information Yield-driven robust circuit optimization usually intractable Developed efficient circuit specific iterative robust optimization algorithm Use constraint maximization to find the worst case variation vector direction Multi-scenario optimization to achieve new robust design Yield monotonically increases with optimization over expanding variability set Problem scales linearly with the number of design specifications

27 Acknowledgements Thanks to Mar Hershenson, Sunderarajan Mohan, Dave Colleran, Almir Mutapcic and Shyne Tseng at Magma Design Automation, Inc. Funded by the Center for Integrated Circuits and Systems at MIT.

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