Impact of Leakage on IC Testing?

Transcription

1 Deep Sub-micron Test: High Leakage Current and Its Impact on Test; Cross-talk Noise Kaushik Roy Electrical & Computer Engineering Purdue University Impact of Leakage on IC Testing? Our Focus Higher intrinsic leakage challenges current based test techniques I DDQ test method well established and widely accepted for defects and is necessary I DDQ testability issue - sensitivity? Novel testing solutions 1

2 Problem Statement Can I DDQ and current based test methods be effective and survive the prohibitive increase in intrinsic leakage posed by technology scaling? How do we discriminate high speed leaky ICs from defective ones? Transistor Leakage Mechanisms Gate I 7 I 8 Source Drain n + I n + 2 I 3 I 6 I 5 I 1 I 4 p-well Short Channel Transistor 2

3 Components of I OFF 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 For a 0.35 micron CMOS Technology weak inversion + pn junction + DIBL + V D = 3.9 V (BI) weak inversion + pn junction + V D = 2.7 V (V DD ) weak inversion + pn junction (80 mv/dec & V D = 0.1 V) pn junction Leakage (I OFF ) Current in Amps Weak inversion = subthreshold 1. No punchthrough 2. No width effect 3. No gate leakage Subthreshold Leakage & SCE dominate I DDQ Testing Measures current in power supply (V DD ) during circuit quiescent state (when all logic states have settled) V DD V in V out i DD V in IDDQ Strobe V i DD out Defect Defect No Defect (control) I DDQ V SS time Choice of input vector matters in complex circuits 3

4 Gate Oxide Defect & I DDQ I DDQ most effective in detecting defects Example: NMOS gate oxide defect creating a V DD to V SS leakage path V DD V DD 0 1 Gate oxide defect V SS V SS Circuits become more susceptible to defects with scaling Single Threshold I DDQ Test Limit Limit Selection: 1. Quality and Reliability 2. Yield Loss and Cost 120 Number of ICs Limit Failure Analysis to verify defects and study outliers E E E E E E E E E E E E-02 I DDQ (A) 4

5 Normal Distribution µp I DDQ Distributions Limit concept on cumulative probability plots (a) (b) Distribution Tail Cum Dist Limit? (a) (b) Short Leff Very Short Leff Main Population I DDQ I SB (ma) State-of-the-art in Current Testing Transient Current Testing [1,2] Current Signatures and Ratios [3,4] Delta I DDQ [5] Divide and conquer techniques [6,7] Forcing stacked transistors by input vector selection [8] Not sufficient to address the problem Our solution not in conflict with above 5

6 References: [1] M. Sachdev, et al., Defect Detection with Transient Current Testing and its Potential for Deep Submicron ICs, Int. Test Conf., pp , Oct [2] E.I. Cole Jr., et al., Transient Power Supply Voltage (v DDt ) Analysis for Detecting IC Defects, Int. Test Conf., pp , Nov [3] A. E. Gattiker et al., Current Signatures, VLSI Test Symposium, pp , [4] P. Maxwell, et al., Current Ratios: A Self-Scaling Technique for Production IDDQ Testing, Proc. of International Test Conference, pp , Oct [5] C. Thibeault, et al., Diagnosis Method Based on Delta IDDQ Probabilistic Signatures: Experimental Results, Int. Test Conf., pp , [6] K. Wallquist, Achieving IDDQ/ISSQ Production Testing with Quic-Mon, IEEE Design and Test of Computers, Fall [7] W. Maly, et al., Design of ICs Applying Built-in Current Testing, J. of Electronic Testing: Theory and Applications, pp , Dec [8] Y. Ye, et al., A New Technique for Standby Leakage Reduction in High- Performance Circuits, Symp. on VLSI Ckts, p. 40, June Parameters Influencing I OFF, I DDQ & Standby Power Substrate (Body) Bias Temperature Lowering Power Supply Voltage Combined Effects 6

7 I OFF / Leakage Reductions Temperature Factor of ~ 350 from room to -50 C Substrate backbiasing (RBB) - V BS Factor of ~ 3000 at ~ 2 V Lowered V DD Factor of ~ 10 from 2.7 V to 1.5 V Multiple V T For a 0.35 micron CMOS Technology Two parameter Test Solution Scaling Functional and Delay Fault Testing I DDQ Components of transistor leakage Leakage reduction techniques Two-parameter test solution Sensitivity enhancement by RBB Sensitivity enhancement by Temperature 7

8 I DDQ tail? Fast or Defective ICs? 95% (a) Cum Dist (b) Discriminate high speed ICs from defective ones (a) (b) Short Leff Very Short Leff % of the ICs are in the I DDQ distribution tail? I SB (ma) I DDQ Intentionally skewed L eff shorter for higher performance I DDQ and F MAX as a function of L e I OFF 1E-04 1E-05 I OFF (A) 1E-06 Normal Distribution F MAX = f(le mean ) 1E-07 1E-08 I OFF is an exponential function of L e. 1E-09 1E L eff (um) - Normalized # of ICs Dominates leakage Dictates performance Le Shorter channel transistors exponentially contribute more to I DDQ I DDQ =f(le min ) Lemin Le mean Le 8

9 I OFF Current and L e Distribution I OFF Normal Distribution F MAX = f (Le mean ) # of ICs I DDQ = f (Le min ) Le min Le mean Le I OFF vs I DDQ Transistor Leakage Circuit Leakage IC Leakage - IDDQ (ua) I DDQ < n I OFFi i= Transistor Leakage - IOFF (na) 9

10 Two-Parameter Test Concept: Leakage vs Speed Defects Upper Limit F MAX vs I DDQ I DDQ F MAX Two-Parameter Test: Decision Table & Adjustable Limit Table 6.1. IC decision matrix for I DDQ and F MAX testing. I DDQ F MAX Decision on IC H H Good - Fast H L Defect L H Unlikely L L Good - Slow 10

11 µp Circuit I DDQ vs F MAX I DDQ Normalized Static SB I I DDQ = f ( I OFF, V T, L e ) F MAX = f ( I D (SAT), V T, L e ) Normalized Maximum Frequency (F MAX ) Empirical relationship derived from existing test methods Data include die-to-die parameter variation Adjustable Limit for I DDQ vs F MAX Normalized Static SB I I D DQ Adjustable Limit Line IC leakier than expected for its speed Defective? Trend Line Normalized Maximum Frequency (F MAX ) Limit may be established by currently available statistical methods 11

12 Two-Parameter Test Practical Limitations Defects Upper Limit Thermal Runaway or Reliability Limit F MAX vs I DDQ I DDQ Single Threshold Limit Adjustable Limit Assumed leakage to frequency dependency F MAX Addressing issues raised by the problem statement High intrinsic leakage Our solution places I DDQ in context of F MAX High I DDQ leakage not an issue in itself High leakage at high speed is OK I DDQ effectiveness and sensitivity Two-parameter test extends I DDQ effectiveness More on improving sensitivity by RBB Discriminates high speed leaky ICs from defective ones 12

13 How does our solution compare to state-of-the-art in I DDQ testing? No extra cost, no new hardware or instrumentation, uses established tests It complements the existing methods such as lowering V DD, lowering temperature, and increasing V T by RBB or multiple V T Two-Parameter Test Leakage in context of Speed Defects Upper Limit Can we detect these defective ICs? F MAX vs I DDQ I DDQ Adjustable Limit Detectable with Two-Parameter testing Assumed leakage to frequency dependency F MAX 13

14 IC Chip Measurements Delay Chain and RO Circuits Leakage Current & Power Measurements on an IC with 20,000 transistors Delay Delay Toggle Toggle Flip Flip Flop Flop FEM 95 Chain Chain MUX MUX Direct measurement of circuit leakage & delay: Delay tracks microprocessor clock frequency change in response to transistor performance change Improving the Sensitivity Two-Parameter Test + RBB and/or T Detectable by RBB or T Detectable with two-parameter testing Original test & its limit I DDQ Test & its limit after RBB or T Don t care defect Defect threshold current F MAX 14

15 Leakage with RBB Normalized IDDQ Leakage (X Ratio) Leakage vs Frequency with RBB NBB RBB Freq RBB Normalized Frequency (X Ratio) NBB lkg 0.5V RBB on average leakage by 1.8X & frequency by 10% Leakage reduction : intrinsic=1.8x & defective=1.45x Sensitivity enhanced by 1.8/1.45=1.25X or 25% 25% improvement not very effective in scaled technologies Normalized IDDQ Leakage (X Ratio) Circuit Leakage Reduction by RBB NBB lkg RBB NBB RBB IDDQ Leakage Ratio (normalized) Normalized Original NBB Frequency (X Ratio) Sensitivity Enhancement by RBB Intrinsic NBB Defective RBB NBB Frequency Ratio (normalized) NBB RBB defect1(nbb) defect1(rbb) defect2(nbb) defect2(rbb) S/N Ratio of Two-Parameter Test What do we mean by S/N ratio? Signal defective IC leakage Noise intrinsic IC leakage Intrinsic leakage noise is predictable RBB & T shifts the intrinsic leakage noise Signal shifts less by RBB or T resulting in widening of spread between S & N Normalized IDDQ Normalized Fmax T=27.7C T=110C Normalized IDDQ T=27.7C T=110C Normalized Fmax Leakage vs Frequency with T Circuit Leakage Reduction by T Focus on leakage reduction only 15

16 Sensitivity Adjustment Normalized IDDQ Leakage (X Ratio) defective intrinsic improved S/N ratio T=27.7C intrinsic room T=110C intrinsic hot hot T=27.7C Defect room T=110C Defect hot hot Normalized Fmax Frequency (X (X Ratio) Improving Sensitivity by T Normalized IDDQ Leakage (X Ratio) T=-50C T=-25C T=0C 1.0 T=27.7C T=50C T=110C Normalized Frequency (X Ratio) Adjusting Sensitivity Leakage reduction: intrinsic=36x & defective=2.6x Sensitivity and S/N ratio enhanced by 36/2.6=13.8X More leakage reduction is possible at a higher cost (T ) Issues in DSM Era Signal integrity DSM defects capacitive and inductive coupling voltage drop - charge share power supply noise functional/delay faults New DSM fault models should support test generation self-test capability IDDQ testabilty Diagnosis 16

17 High Speed Circuit Testing for Cross-Talk Defects Crosstalk -- One of the major noise injection mechanisms in DSM circuits Determine nodes that are susceptible to these faults in high-speed circuits. Helps to generate the test pattern. Provide guidelines to design noise tolerant circuits Noise Sources in DSM Circuits Cross-talk coupling Power supply noise Charge redistribution 17

18 Why Noise Modeling? To determine the circuit immunity to noise. Helps in designing noise tolerant circuit. Reduces the number of nodes to be tested. Static Noise Margin V DD NM L = V IL - V OL V OH NM H = V OH - V IH V IH V IL V OL 0 V OL V IL V IH V OH V DD 18

19 Requirement of New Technique New technique for testing of high-speed DSM monotonic logic circuits Dynamic Noise Modeling Static NM - not sufficient Dynamic NM - new metric to check functional violation Detection of functional/delay faults in a circuit Estimate propagated noise at a victim node Comparison with dynamic noise margin Analysis of noise immunities of high speed circuits High Speed Circuit Testing for Cross-Talk Defects Crosstalk -- One of the major noise injection mechanisms in DSM circuits Determine nodes that are susceptible to these faults in high-speed circuits. Helps to generate the test pattern. Provide guidelines to design noise tolerant circuits 19

20 Dynamic Noise Model Linear relation : i o ( vi ) = gm ( vi Von ) : vi Von Ga aggressor Cc Von v(t) ( v( t) V ) Q = g dt t m on Q t > C f NM f?? Gd Gv Gf drive Cv victim Cf affected Vd Dynamic noise margin : NM C f g m f (volt sec) Simulation Based Verification Domino OR gate For gm rectangular ( vnoise Von) dtnoise input = NM f C v ( v V ) noise noise f on NM f T = g C m NM f C f 1 = + V g m T f on vnoise vnoise T - 4 Input - 16 Input vout = NM f ISO-static NM contour plot Linearity! Different gates with different noise inputs 20

21 Algorithm: Testing for Functional Faults GATE Library CIRCUIT LAYOUT CIRCUIT Levelization / R,L, & C Extraction Static Timing Analysis DNM calculation Coupled noise : V noise (t) Propagated noise Propagated Noise > DNM? Testing for Functional Faults A 4 bit full adder circuit is verified Propagated Noise vs. DNM 3 possible fault sites Noise Peak vs. DC NM 12 possible fault sites Results are also verified with HSPICE simulation DNM Based Verification Can help in reducing the cost for testing. 21

22 Delay Faults Ga aggressor Cc Von v(t) Vout(t) t + del(gv) + Delta Gd Gv drive Cv Vin(t) victim v(t) Coupled Noise Voltage Vd Vin(t) del(gv) Delta Victim Gate Input Transition Gate Delay Delay induced due to coupling C c can be qualitative measure for delay fault New layout architecture can help in reducing delay fault probability through C c minimization Conclusions Two-Parameter test with speed-adjusted leakage limit has a better S/N ratio It discriminates high speed leaky ICs from defective ones Reverse Body Bias (RBB) enhances the test sensitivity (S/N ratio) modestly Temperature improves the sensitivity by more than an order of magnitude (14X) 22

23 Conclusions Cross-talks faults are becoming increasing important for high-speed DSM circuits There is a need for good test and verification methodology for cross-talk defects 23