CIRCUITS. Raj Nair Donald Bennett PRENTICE HALL

Transcription

1 POWER INTEGRITY ANALYSIS AND MANAGEMENT I CIRCUITS Raj Nair Donald Bennett PRENTICE HALL Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown Sydney Tokyo Singapore Mexico City

2 C O N T E N T S Preface Acknowledgments About the Authors Contributors xv xxi xxiii xxv Chapter 1 Power, Delivering Power, and Power Integrity Electromotive Force (emf) Force-Voltage Analogy Electrical Power Physical Analogy for Power Sources of Electrical Power Powering Electrical and Electronic Circuits and Systems Power Delivery Central DC Power Delivery Module Integrated Power Delivery Power Distribution Networks Power Delivery Regulation Power Integrity (PI) Contributors to PI Degradation Exercises 17 References 18 Chapter 2 Ultra-Large-Scale Integration and Power Challenges Exponential Integration and Semiconductor Scaling Microprocessor Architecture Power Trend Scaling of Transistor Dimensions and Its Impact Power and Energy Consumption Power and Energy Expenditure in Charging a Capacitor 28 vii

3 viii Contents Other Sources of Power Consumption 34 Short-Circuit Current 34 Charge Sharing and Interconnect Capacitance 35 Leakage Power, Heat, and Power Integrity Challenges Power Integrity and the Impact of Scaling 40 Loop Inductance Scaling 44 Resistance Scaling Exercises 50 References 51 Chapter 3 1С Power Integrity and Optimal Power Delivery Power Transfer and Efficiency Maximum Power Transfer Theorem С Power Supplies 55 Linear and Switching DC-DC converters 55 Linear Regulators 56 High-Bandwidth Linear Regulators 57 Switching DC-DC converters 60 Voltage References Supply Noise and the Differential Nature of Closed-Loop Power Transfer Noise and Total Power Integrity 72 Resistance, Capacitance, Inductance, and di/dt 72 Resistance 73 Inductance and di/dt 74 Capacitance and System-Level Effects Optimal 1С Power Delivery: On-Chip Inductance and Grid Design Equivalent Circuit Model for On-Chip Power Grid Analysis 81 Full PEEC versus Simplified PEEC Noise Dependency on Slope of Load Current and Capacitance Position 83 Current Slope versus Noise Amplitude 84 Decap Size and Position 85 Qualitative Discussion on Current Slope and Capacitance Placement 85 Analysis of Decoupling Capacitance Position in Frequency Domain Power Grid Analysis Focusing Distribution of Power Consumption 89 Without Decoupling Capacitance 90 With Decoupling Capacitors 91

4 Contents Power Grid Design for Robustness with On-Chip Inductance 94 Power Grid Pitch and Wire Area 94 Spacing between Power and Ground Wires Power Grid Cost Factor Trade-off Analysis and Design Cost Factors for Power Di stribution Grid Design 100 Power Grid Inductance 100 Power Grid Resistance 101 Power Grid Area Ratio Trade-off Analysis for Power Distribution Grid Design Exercises 106 References 107 Chapter 4 Early Power Integrity Analysis and Abstraction Process, Voltage, and Temperature: Design Verification Space Supply Variability Allocation Back-End and Front-End PI Analysis Gaps in 1С PI Analysis Front-End PI Analysis Abstraction of Chip Components 118 On-Chip Power Grid Abstraction 120 Circuit Block and Decoupling Capacitance Abstraction 123 System-Level Characteristics Simulation Environment for Models of High Abstraction Levels Continuum Models Abstraction and PI Analysis Examples Optimal On-Chip Power Network Design System-Level Front-End Simulation Summary and Enhancements Exercises 136 References 138 Chapter 5 Power Integrity Analysis and EMI/EMC Introduction Analysis of Noise Generation and Propagation through a Power Distribution Network Sources of Power and Ground Noise Calculating the Target Impedance of a PDN Estimation of Power-Ground Noise from PDN Impedance 147

5 Contents Modeling Decoupling Capacitors for Noise Mitigation in PDNs On-Board Decoupling Capacitors On-Package Decoupling Capacitance On-Chip Decoupling Capacitors 152 Current Design Methodology for Power Delivery Networks Step 1: Reduce the PDN Inductance as Much as Possible Step 2: The Use of Board Decoupling Capacitors Step 3: The Use of Package Decoupling Capacitors Step 4: Use of On-Chip Decoupling Capacitors 158 Modeling Methodologies Approximations Based on Lower Frequency Higher-Frequency Methods Classification of Numerical Methodologies A Case Study to Compare Numerical Methods 166 Numerical Methods Integral Equation Methods 170 Method of Moments Differential Equation Methods 173 Finite Difference Methods 173 Power and Signal Delivery Analysis Tools and Limitations Limitations Based on Tool Categories Illustration of Tool Limitations 179 Cross-Coupling Characteristics 180 Power Supply Impedance Characteristics 182 Causality Challenges 184 Frequency Sweep and DC Extrapolation Challenges 186 Power Integrity-Aware Electromagnetic Interference Analysis Components of a PDN and Associated Power Integrity Issues System-Level Power Rail Noise Due to SSO/SSN High-Current Transients Package and PCB Plane Resonance System-Level Decoupling Optimization Return Reference Plane Discontinuity 195 Strengths and Limitations of Existing Early EMI methodologies 197 Early Power Integrity-Aware EMI Modeling and Analysis Flow Components of an Early Power Integrity-Aware EMI Flow 199 Layout Creation, Extraction, and Model Abstraction 200 Die-Level Optimization (Dynamic and AC Analyses) at System Level 205 Conducted/Radiated EMI Analysis at System Level 211

6 Contents 5.11 SI, PI, and EMI Summary Exercises 216 References 216 Chapter 6 Power Distribution Modeling and Integrity Analysis Introduction Modeling of a Power Distribution Grid Numerical Analysis of Power Distribution Model Differential and Common-Mode Noise Verification and Error Analysis Modeling of On-Chip Bus Switching Current Verification of the Bus Model Bus Skewing to Reduce Power Distribution Noise Case Study: Reduction of Power Distribution Noise Exercises Appendix: Coefficients for Equation (6-37) 253 References 255 Chapter 7 Effective Current Density and Continuum Models Circuit and Model Simplification Definition of Effective Current Density Effective Current Density and Virtual Currents Symmetry in Networks Containing Conductors, Insulators, and Other Components A Continuum Model Using ECD Practical Application of a Continuum-Based Simulator to 1С Floorplanning Continuum Models Compared to SPICE Models Model Enhancement for Nanoscale CMOS Integrated Circuits Exercises 285 References 286 Chapter 8 Power Integrity-Aware Chip Floorplanning and Design Design for Power Integrity: Nanometer Era Considerations System Requirements Die Cost Performance 290

7 xii Contents Power Minimization Other Considerations Design for Power Integrity: Techniques Power Consumption Management Power Grid Design Chip Floorplanning and Decoupling Capacitance Power Management and Power Integrity Power Management Techniques 302 Clock Gating 302 Multi-V t Libraries 303 Body Biasing 305 Voltage Islands/Power Domains 305 Power Gating 305 Adaptive Voltage Scaling/Dynamic Voltage Scaling Power Integrity Implications 308 References 314 Chapter 9 Power Integrity Management in Integrated Circuits and Systems Chip-Level PI Management Primary Techniques 318 Resistance 318 Inductance 318 Capacitance On-Chip Noise Measurement and Modeling 319 Channel Length of On-Chip Decoupling Capacitance (DECAP) 321 Impact of Well Structure on Noise Voltage-Dependent Decoupling Capacitance 326 Charge and Energy in Voltage-Variable Capacitance Advanced Aspects and Techniques 330 Leakage 330 Architecture and Circuit Techniques System-and Package-Level PI Management System-Level PI Management 331 Power Delivery Path Impedance Package-Mounted Capacitors 334

8 Contents Active Packaging and Active Noise Regulation 335 Charge and Energy Multiplication 336 Copious Charge Flow for Noise Minimization 337 High Bandwidth Local Regulation 337 PI Enhancement with ANR Implementation Package PI Management Summary Exercises 341 References 343 Additional Reading 346 Chapter 10 Integration Technologies, Trends, and Challenges 347 ЮЛ Chip-Level Integration Device Architecture for Low-Power Systems 348 The Double-Gate MOSFET 348 The MIGFET Beneficial Applications of Multiple Independent-Gate FinFETs 350 SRAM 350 Low-Power Circuits for Analog Device Architecture Summary Package-Level Integration 352 Packaging Technology Development Vectors Advanced Packaging Technologies 354 Wafer-Level Packaging 354 System-in-Package 356 Stacked-Die Packages 359 Package-on-Package (PoP) 360 Through-Silicon-Vias (TSVs) 362 Packaging Integration Summary and Challenges Integration Trend for Power Integrity Management Components 366 References 367 Additional Reading 369 Appendix A ECD Continuum Model Derivation 371 Appendix В Derivation of the Helmholtz Equation for Planar Circuits 383 Index 385