EMI Reduction on an Automotive Microcontroller

Transcription

1 EMI Reduction on an Automotive Microcontroller Design Automation Conference, July 26 th -31 st, 2009 Patrice JOUBERT DORIOL 1, Yamarita VILLAVICENCIO 2, Cristiano FORZAN 1, Mario ROTIGNI 1, Giovanni GRAZIOSI 1, and Davide PANDINI 1 1 STMicroelectronics, Agrate Brianza, Italy 2 Politecnico di Torino, Torino, Italy

2 Outline Design for EMC: motivation EMC-aware design on an automotive microcontroller EMI simulation framework: characterization and modeling Conducted and radiated emissions: simulations vs. measurements Conclusions 2

3 EMC for Automotive More complex systems Control units Interfere with local bus 100MHz Interfere with Mobile 0.9,1.8,1.9GHz Interfere with Computer 2.5Ghz Interfere with local bus 100MHz 3

4 Electronics in Automotive is Everywhere Cluster / Body Car Radio Entertainment GPS Suspensions - ABS Engine Mngt Transmission - Gear Airbag (safety in general) 4

5 Electronics in Automotive is Increasing More devices More functions More bus communication More mounting locations Increase of complexity Increase of quantity Increase of EMI 5

6 EMC Automotive System Overview Project Development Phase While in the past EMC was addressed mostly at vehicle level nowadays it has to be improved at all levels 6

7 IC/Component Selection for EMC source coupling path victim Cost Optimization capabilities EMC problems solved at the source cause the lowest costs and the most effective solutions! EMC problem solving at the coupling path or load is expensive, ineffective and sometimes simply not possible! 7

8 EMC Handled at the End of the Design Cycle DESIGN Architectural Design FABRICATION Version n Floorplan Synthesis Place&Route Verification EMC Measurements Compliance? NO YES + n months months + $$$$$$$$ $$$$$$$$ Done 8

9 Our Vision: EMC-aware Design Architectural Design DESIGN EMC Tools EMC Training EMC Design Guidelines Floorplan Synthesis and Place&Route Verification EMC Models EMC Simulations Compliance? NO YES FABRICATION EMC compliant 9

10 Low-EMI Design To reduced power rail noise on-chip decaps (i.e., fillercap cells) are used How many? Where? Important to know their frequency behaviour Important to place them close to the hot spots to maximize their damping effect on power rail noise Design methodology for decap insertion is necessary for efficient and cost-effective low-emi design On-chip decaps are usually built with MOS transistors with long and wide channels to get a sufficiently large capacitance Standard practice uses these decap cell topologies V DD V DD MOS cell GND GND Tie-off cell 10

11 Fillercap Characterization: Frequency Behavior *0.18μm CMOS envm 2.2GHz 10GHz 110GHz 11

12 Fillercap Frequency Behavior Trend *90nm CMOS envm 72.55MHz 327.3MHz 143.8GHz 12

13 Test Case: STXX STXX: typical microcontroller for automotive applications Technology in 0.18μm envm CMOS technology where the NVM devices are shrunk to 0.13μm Analog-to-Digital Converter, 128K EEPROM, ROM, SRAMs, Voltage Regulator, etc. Different power supply domains 13

14 Power Supply Waveforms Gate-level Simulations Digital power supply I/O PAD waveforms estimated by Apache s RedHawk (including package model) 14

15 Power Supply Waveforms Gate-level Simulations Digital power supply I/O PAD waveforms estimated by Apache s RedHawk (including package model) I/O PAD 2 nd Harmonic Reduction (dbμv) 2 nd Harmonic Reduction (%) i_vcap nd harmonic (@48MHz) Amplitude reduction (dbμv) 15

16 System Power Distribution Network Model To develop an EMI simulation framework it is necessary to model the complete system power distribution network (PDN) A real system PDN consists of chip, package, and board The combined effects of chip, package, and board must be considered to accurately analyze both power/ground integrity and EMC Capacitor Chip Capacitor Voltage Regulator Package Capacitor Printed Circuit Board 16

17 System Power Distribution Network Model In an EMI simulation framework the system PDN (board+package+chip) must be represented by a SPICElevel compact lumped RLC circuit I(t) Volt. Reg.+Board+Package Chip But we also need to consider non-uniform switching, circuit size/frequency and decoupling parasitics Hence we need more accurate models to capture all these effects 17

18 EMI Simulation Framework To develop an efficient and accurate methodology for noise and EMI estimation at IC and PCB level for fast assessment of chip EMC behavior before tape-out To enable IC and package designers to achieve chip and IC-package design (co-)optimization for EMI reduction To enable board designers to optimize PCBs for EMI reduction and system-level power integrity An EMI simulation framework is a critical enabler of an EMC-aware design methodology and is based on availability of accurate and compact EMI models for chip, package, and board EMI modeling requirements: Early availability during IC and PCB design Layout- or netlist-based High accuracy at low complexity Capability to include IP macroblocks Easy integration into chip and board SI/PI simulators Based on IEC standards Widely accepted format (i.e., SPICE-like) 18

19 EMI Simulation Framework: Components Characterization Standard Cell Characterization Macroblock Characterization IO Ring Characterization Chip Model Modeling Voltage Regulator Model Package Model Board Model Probe/TEM Cell Model 19

20 EMI Simulation Framework: Characterization Standard cell characterization Macroblock characterization IO ring characterization Power rail noise analysis needs a specific characterization to generate the current profile for each standard cell Power rail noise analysis needs a specific characterization to generate the current profile for each macroblock (SRAMs, ROMs, eflashs, eeeproms, ADCs, etc.) Noise characterization for the IO subsystem Apache RedHawk Apache Totem-MMX Apache Sentinel-SSO 20

21 EMI Simulation Framework: Modeling Chip modeling Package modeling Board modeling Compact model representing the entire chip (core, macros, IOs, decaps) in terms of passive elements and current sources Apache CPM with RedHawk Chip model obtained after power rail noise analysis for all power supply domains (multi-power supply domain supported) Spice-level RLC netlist representing the package wire bonding, pins, lead frames Ansoft Q3D and HFSS Apache PakSi-E SPICE-level RLC netlist representing the board traces and ground planes Sigrity PowerSI and Broadband SPICE Can extract the SPICElevel netlist for each trace from the PKG to the connector Can model the whole board Apache Sentinel-PI IC-PKG-PCB co-analysis platform for system-level power integrity 21

22 Apache s Compact Power Model (CPM) Apache s CPM (obtained with RedHawk) models the chip PDN by means of an equivalent admittance connected to a current generator Chip PDN equivalent admittance representation p1 p2 Y Chip I(t) Piecewise linear switching current representation p1 0 p2 CPM extracted from STXX Icursig1 p1 p2 pwl( ps ps ps ps ) 22

23 CPM: Validation Apache s RedHawk vs. CPM w/o and w/- on-chip decaps Good accuracy of CPM (ELDO transistor-level simulations) against RedHawk (gate-level analysis) results W/o decaps W/- decaps 23

24 Chip, Package, and Board System Voltage Regulator Model Board Model Package Model Compact SPICE Model Chip Model 24

25 Voltage Regulator Modeling The output impedance of the voltage regulator (VR) was obtained with the linear model proposed by Crovetti and Fiori* considering the average current required by the STXX design (10mA**) over the current full range (0-50mA**) * P. Crovetti and F. Fiori, A Linear Voltage Regulator Model for EMC Analisys, IEEE Transactions on Power Electronics, vol. 22, pp , Nov ** STXX Design Objective Specification, System to Silicon, S2SDL01110 Rev. 3.0, Mar

26 Board Modeling A PCB compact SPICE model was obtained using the Sigrity s SPEEDXP toolsuite PowerSI - frequency-domain electrical analysis of IC packages and PCBs Broadband SPICE - conversion of N-port network parameters to SPICE circuits STXX PCB used for EMC measurements 26

27 Probe/TEM Cell Modeling Radiated emission measurements TEM Cell 50Ω adapted system L TEM1 R M K 1 Conducted emission measurements Spectrum analyzer 50Ω adapted system C TEM L TEM2 K 2 R C IN M 120Ω L TEM1 L TEM2 R M R IN 10nH 10nH 50Ω 50Ω K K C TEM C M 6.8nF 51Ω 8pF 100fF Impedance matching network 50Ω 27

28 Conducted Emissions at PCB J3 Test Pin J3 BOARD STXX TQFP80 IO5 VDD 5V 28

29 J3 Test Pin SMA Waveform Simulation 29

30 J3 Test Pin SMA Waveform Simulation PCB Test Pin 2 nd Harmonic Reduction (dbμv) 2 nd Harmonic Reduction (%) J nd harmonic (@48MHz) Amplitude reduction (dbμv) 30

31 J3 Test Pin Spectrum: Simulation vs. Measurement J3 Voltage [dbμv] Frequency [Hz] 31

32 System Model for Radiated Emission Simulations TEM cell model CPM model PCB model PKG model 32

33 Radiated Emission Measured Voltage [dbμv] Frequency [Hz] 33

34 Radiated Emission Measured vs. Simulated Voltage [dbμv] Max Radiated Emission: measured vs. simulated difference: 0.4 dbμv Frequency [Hz] 34

35 Conclusions We proposed an EMC-aware design methodology A significant on-chip EMI reduction was achieved! This methodology was successfully exploited for the tape-out of a microcontroller for automotive applications An EMI simulation framework accounting for both the conducted and radiated emissions of the IC-PKG-PCB system was developed The simulated emissions of the entire system were compared with the available measurements The comparison of simulations vs. measurements demonstrated the effectiveness and the accuracy of the EMI simulation framework The proposed simulation framework is a competitive solution for accurate EMI evaluation and minimization before tape-out and allows to predict the true post-silicon EMC behavior vs. increasingly aggressive EMC targets dictated by marketing, customers, and international standards 35