Modeling the Radiated Emission of Micro-controllers

Transcription

1 Modeling the Radiated Emission of Micro-controllers Etienne Sicard Christian MAROT André PEYRE LAVIGNE Claude HUET Etienne SICARD AUTOMOTIVE SA 1

2 Contents 1. Context of the study 2. System design methodology for EMC 3. The IERSET project on EMC for ICs 4. Core emission model 5. Emission model with Ios 6. Emission model in TEM cell 7. Conclusion 2

3 1. Context of the study µm, 2 metal layers Up to 100,000 devices on a chip CPU frequency 50MHz 0.12µm, 6 metal Up to 200,000,000 devices CPU frequency 1GHz IC 40 pins 10 years of evolution 1000 pins 3

4 1. Context of the study Voltage & Current Scaled current Current di/dt di/dt Voltage Voltage supply decreases Current amplitude keeps constant Faster switching Stronger di/dt di/dt Time Increased EMC problems 4

5 1. Context of the study Low parasitic emission is a key argument dbµv Supplier A FM RF GSM Not EMC compliant 60 40dB 10dB Supplier B Probably EMC compliant Ultimate target MHz 5

6 1. Context of the study Example for automotive Interference with local RF & Bluetooth links 433 MHz, 2.5GHz Parasites internal devices (ABS) Similar EMC problems in aerospace Interference with mobile phone 900, 1800,1900MHz 6

7 2. System Design Methodology for EMC Obsolete Design Methodology System on chip specification DESIGN Architectural Design Design Entry Design Architect FABRICATION Version n Version n EMC Measurements Compliance? + 6 months + $$$$$$$$ NO GO GO EMC compliant 7

8 1. 2. System Context Design of the study Methodology for EMC Obsolete Design Methodology db peaks frequency PCB design Prototype board EMC scan Electromagnetic incompatibility found too late 8

9 2. System Design Methodology for EMC Target Design Methodology System on chip specification Training Architecture Guidelines Tools DESIGN Architectural Design Design Entry Design Architect Design Guidelines IC Models EMC Simulations Compliance? GO FABRICATION EMC compliant 9

10 2. System Design Methodology for EMC Target Design Methodology With IBIS With IBIS and core model PCB design Wrong prediction of the radiated emission Good forecast of radiated emission A core model is mandatory for accurate emission prediction 10

11 2. The IERSET project European Research Centre on Electronics for Transportation identifies and co-ordinate co-operative research. Project EMC for ICs AIRBUS AUTOMOTIVE SA TOULOUSE Objectives Definition and validation of a model to be used in PCB CAD tools to guarantee the EMC of electronic systems One model from 1MHz to 1GHz, for conducted and radiated emission 11

12 2. The IERSET project ICEM (Integrated Circuit Electromagnetic compatibility Model) Draft standard Commitee Draft for Voting Technical work at IERSET Toulouse, France UTE France 02/2001 ICEM Cookbook version 1.c aug / /

13 2. The IERSET project ICEM presentations Presentation Presentation Presentation Presentation Presentation Paper IEEE Pack. Paper IEEE EMC IBIS summit Munich IEC 93 Singapoure IBIS meeting EMC compo Pres. to Mentor Toulouse Pres to Zuken CEM 02 Grenoble Date 02 Paris IBIS meeting IEC 93 EMC Europe 03/01 09/01 01/02 03/02 09/02 13

14 4. Core Emission Model ICEM includes a simple core model, not handled by IBIS External VDD Rvdd Lvdd dbµv Peak harmonics Cd Cb Ib Secondary resonance 40 Primary resonance External VSS Rvss Lvss Basic parameters IC model Cd, Ib Advanced param. R,L,Cb Measurements Simulation Cd, Ib All parameters 1 10 f (MHz)

15 4. Core Emission Model Current generator estimation Physical Transistor level (Spice) Interpolated Transistor level (Powermill) Gate level Activity Huge simulation Limited to analog blocks Difficult adaptation to usual tools Limited to 1 M devices Simple, not limited Fast Not very accurate Activity ( nb nodes) Activity of D60 CPU based on Verilog simulations over 1 clock cycle (125ns): Number of nodes switching in the same ns D60 CPU Equivalent Current generator Ib time (ns)

16 5. Emission Model with IOs Validation for a 16 bit micro-controller dbµv in conducted mode Within 10dB, but I/Os not handled Measurement (Conducted 1W) Simulation (PSPICE) EMC model 1 10 f (MHz) Comparison between simulation and measurement on a 16 bit micro-controller 16

17 5. Emission Model with IOs Add IBIS I/O data Core VDD Rvdd Lvdd I/O VDD Cd Cb Ib Cio I/O Core VSS Rvss Lvss Zsub I/O VSS Zsub: basically a 1-10Ω serial resistance Cio : decoupling capacitance for IO supply IO block: reuse of IBIS 17

18 5. Emission Model with IOs Validation IO modify the spectrum at high frequencies (>300MHz) 18

19 6. Emission in TEM cell Proposed model: capacitance & inductance coupling To PCB Lpackage Cdie_gnd Chip under test 50 Ω 50 Ω KCoupling Cdie_septum PCB Chip under test Lseptum Receiver 19

20 6. Emission in TEM cell Validation for the core alone Model fits correctly up to 400MHz At high frequencies, close from noise floor 20

21 6. Emission in TEM cell Validation for the core & IOs Model fits correctly up to 800MHz At high frequencies, IO effects dominate 21

22 Conclusion Technology scale down illustrated More complex chips increase parasitic emission An EMC model for Ics is mandatory A simple model has been proposed Satisfactory prediction of conducted emission Prediction of the core emission in TEM investigated Model proposal standardized by UTE (ICEM) Presentation and promotion to CAD & IC providers 22