ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY

Transcription

1 ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY Rémy FERNANDES Lead Application Engineer ANSYS ANSYS, Inc. February 2, 2018 ANSYS

2 ANSYS - Engineering simulation software leader Our industry reach and solution offerings Leading Disciplines Structures Thermal Systems Fluids Electromagnetics Power Integrity Embedded Software Global Reach PEOPLE CUSTOMERS 1, ,000+ GLOBALLY 2,000+ FROM CHANNEL PARTNERS Industry Presence Automotive Academic Consumer Goods Energy Industrial Equip. & Rotating Machinery Aerospace & Defense Construction High-Tech Healthcare Materials & Chemical Processing ANSYS, Inc. February 2, 2018 ANSYS

3 AGENDA Trends and Challenges of Electronics Industry ANSYS Chip-Package-System ANSYS SIwave : SI, PI simulation overview Demo ANSYS, Inc. February 2, 2018 ANSYS

4 Key Trends In Electronics Industry Miniaturization Embedded Software Mobility and Wireless Connectivity Power Efficiency Faster Communication ANSYS, Inc. February 2, 2018 ANSYS

5 Challenges Electrical reliability Thermal reliability Structural reliability Signal integrity Power integrity Electrostatic discharge Electromagnetic emission Electronics cooling Fast hotspots determination Board deformations Vibrations analysis Delamination Fatigue ANSYS, Inc. February 2, 2018 ANSYS

6 V_vline Time [ns] v_line3 V_line l_slot 160mm Curve Info V_vline Setup1 : Transient XY Plot 8 l_slot 160mm Time [ns] Curve Info v_line3 Setup1 : Transient v_line XY Plot 7 l_slot 160mm Time [ns] Curve Info v_line2 Setup1 : Transient v_line v_line Time [ns] XY Plot 8_1 XY Plot 6 l_slot 160mm l_slot 160mm Curve Info v_line1 Setup1 : Transient Time [ns] Curve Info v_line4 Setup1 : Transient Electrical reliability Signal & power integrity Electrostatic discharge Electromagnetic emission ANSYS, Inc. February 2, 2018 ANSYS

7 Thermal reliability Hot spots Resistive heating of traces Flow pattern ANSYS, Inc. February 2, 2018 ANSYS

8 Structural reliability Trace mapping Exact deformations and stresses ECAD Optimal vibrational behavior Successful passing of the drop test ANSYS, Inc. February 2, 2018 ANSYS

9 ANSYS Solution Geometry Based Reliability Design Multiphysics simulation of printed circuit boards Electro-Thermal Stress Analysis ECAD Design Electrical Reliability Thermal Reliability Power and Signal Integrity Analysis Joule heating Losses Temperature Field Thermal Analysis Temperature Field ANSYS SIwave ANSYS Icepak Mechanical Reliability Stress Analysis ANSYS Mechanical ANSYS, Inc. February 2, 2018 ANSYS

10 ANSYS Electronic Business Unit Driving CPS : Chip-Package-System Convergence Digital RTL PowerArtist CHIP RedHawk PACKAGE Siwave, HFSS,Q3D, Icepak, Mechanical BOARD Siwave, HFSS,Q3D, Icepak, Mechanical DDR RF Analog IPs Totem HDMI FLASH CONNECTOR HFSS, Q3D, Mechanical End-to-End Chip-Package-System Power, Noise, Thermal, EMI, Timing Platform ANSYS, Inc. February 2, 2018 ANSYS

11 ANSYS Technologies for Electronic Systems ANSYS, Inc. February 2, 2018 ANSYS

12 ANSYS SIWAVE FOR SIGNAL AND POWER INTEGRITY ANSYS, Inc. February 2, 2018 ANSYS

13 ANSYS Typical SI/PI Design Flow Electronic Design Environment (Cadence, Mentor, Zuken, Altium...) EM Simulation & Extract Parasitics Database Import Geometry, Stack up, Components Circuit Simulation EM Model Spice S Parameter Verilog-A IBIS 5 IBIS AMI ANSYS, Inc. February 2, 2018 ANSYS

14 DC Power Design Application Example Objective: DC Power Solution All ICs require DC power to operate. It is common for layout engineers to inadvertently cause DC shorts and use too few vias when designing PDNs. ANSYS Solution Use SIwave to predict DC power distribution problems that result in respinning PCBs. This solution finds current bottlenecks, predicts high power losses, and large voltage drops Use bidirectional link with Icepak to determine thermal effects Value of Simulation The simulation of DC power using ANSYS starts with design concepts, includes the influences of manufacturing, and allows detailed evaluation of the power delivery network, signal net routing, connector and via breakouts ANSYS, Inc. February 2, 2018 ANSYS

15 DC Results & Analysis 0.99mΩ 0.96mΩ DC Path Resistance Current Vectors Showing Electron Direction Power & Ground Plane Voltage Drop SIwave Thermal Solves using Icepak ANSYS, Inc. February 2, 2018 ANSYS

16 Timing Analysis Application Example Objective: High Density & High Speed Develop modern electronic devices with greater density of SDRAM (larger RAM) using even-faster speed devices. ANSYS Solution Performs timing analysis that includes signals & PDN Performs fast flight time analysis Performs virtual compliance for memory busses Value of Simulation The simulation of memory, high speed serial links using ANSYS starts with design concepts, includes the influences of manufacturing, and allows detailed evaluation of the power delivery network, signal net routing, connector and via breakouts ANSYS, Inc. February 2, 2018 ANSYS

17 Signal Net Analyzer Impedance & Flight Time Calculations Driver IC U1.(pin)25 Void A on return current path U7.(pin)60 Receiver IC Void B on return current path A digital signal SNA provides: 1. Z o Profile & Delay for all paths of a signal. Zo@ void A Zo@ void B 2. Reflection Noise through transient analysis. Characteristic Impedance Voltage waveform at receiver IC ANSYS, Inc. February 2, 2018 ANSYS

18 Building the Channel Single environment allows extraction of component models such as vias, connectors, and transmission lines as well as concatenating these and other models into a channel schematic S-parameters, eye diagrams, and bit error rate of channel can be simulated Individual components can be optimized and channel results updated quickly TX RX ANSYS, Inc. February 2, 2018 ANSYS

19 Frequency Domain Channel Analysis Simultaneous component- and system-level accuracy allows rapid evaluation of tradeoffs In this example a change from stripline to microstrip improves loss at the expense of crosstalk ANSYS, Inc. February 2, 2018 ANSYS

20 Time Domain Channel Analysis Closed eye at receiver with the stripline topology Open eye at receiver with redesigned microstrip topology. Eye at reference receiver on Stripline topology EH: 62mV ANSYS, Inc. February 2, 2018 ANSYS Eye at reference receiver on improved Microstrip topology

21 AC PDN analysis Application Example Objective: High Density & High Speed Develop modern electronic devices with greater density of SDRAM (larger RAM) using even-faster speed devices. ANSYS Solution Model power delivery networks and noise propagation on PCBs Automates decoupling capacitor selection, placement and optimization Predicts capacitor placement effectiveness by analyzing loop return currents Use CPM models to predict chip performance to complete system-level simulation Value of Simulation Simulation of memory using ANSYS starts with design concepts, includes influences of manufacturing, and allows detailed evaluation of power delivery network, signal net routing, connector and via breakouts ANSYS, Inc. February 2, 2018 ANSYS

22 Power Integrity Analysis Designs of today operate in conjuction with a number of clocks, oscillators, power supplies, and signaling standards. Supplying sufficient power means designing a Power Delivery Network capable of handling any perturbations or irregularities that these complex systems demand. The example below shows voltage for both the time and frequency domain simulation results of a memory interface. A good design will minimize the voltage ripple to ensure that all active devices have a stable and reliable voltage reference. Excessive perturbations in power could cause adverse affects to input and output margins or even couple to other power rails. 873 mv pk-pk due to 200 MHz PRBS ANSYS, Inc. February 2, 2018 ANSYS

23 Supplying Power VRM Transient Simulation Setup Voltage Regulator Module (VRM) is modeled with a series source resistance of 5mΩ for this example. Active Device is modeled as a Current Sink 1A Amplitude: I pk pk = 2A Frequency = 5 MHz Time Delay = 1μs VRM Active Device Example V ripple = I (5MHz) Z (5MHz) V ripple = 5mV = 10mV pk pk ANSYS, Inc. February 2, 2018 ANSYS

24 Supplying Power VRM Frequency Domain Response At DC, Z 11 = 5mΩ which is the VRM series resistance. At f, Z 11 due to the path loop inductance. In this case, a total of 11pH V 0.01n 1p RZ=0.1ohm Z 11 Example V ripple = I (5 MHz) Z (5 MHz) V ripple = 1A 5mΩ V ripple = 5mV = 10mV pk pk ANSYS, Inc. February 2, 2018 ANSYS

25 Early PI Investigations : Auto Select Capacitor Define a VRM Model + PCB using ESR and ESL parameters : Red curves Define an Impedance Mask as Target or Load it Filter Capacitors Vendors, Series, EIA size and run the AUTO ANSYS, Inc. February 2, 2018 ANSYS

26 Simulation of Physical Structures Circuit Simulation vs. Electromagnetic Field Solvers Real, physical designs have many more inductive loops, capacitive planes, and resistive paths which were not depicted in the previous example circuit. In order to account for all of the effects of physical layout and geometry complexities, a field solver such as Siwave or HFSS must be used. In any of the methods shown, loop inductance plays a vital role in determining the frequency of effectiveness. The L-C combination dictates the resonant frequency of adding or changing a capacitor value at a specific location. 1 f resonance = 2π LC Equivalent Series Resistance (ESR) and conductor path resistance affects the quality factor (Q) of the placed component. 1 2πfC Active Device Q = ESR VRM VRM Active Device ANSYS, Inc. February 2, 2018 ANSYS

27 Resonance Simulation Eigenmode analysis identifies location and frequency of natural cavity resonances that exist between planes Scans entire PCB/PKG on all layers If a resonance is excited, Signal Integrity can be compromised : High Z, null in S21, EMI etc. Resonances should be moved away from critical parts and outside operating frequency Reducing Resonance : Resonances always exist but you can reduce their impact by: Changing the decoupling scheme Changing the stackup Changing plane dimensions Adding via stitching Moving discrete parts ANSYS, Inc. February 2, 2018 ANSYS

28 SIwave SYZ Analysis Setup to extract [S], Z vs Freq To Perform a circuit extraction or SI analysis, place ports in desired location Ports are similar to probes in lab measurements ANSYS, Inc. February 2, 2018 ANSYS

29 Z11 Power Delivery Network Impedance Full-wave extraction of entire PDN including: Board geometry Passive components : Turn ON or OFF decaps Bare PCB With Capacitors ANSYS, Inc. February 2, 2018 ANSYS

30 PI Advisor: Automated PI Analysis Optimizes Decoupling Capacitors for Power Integrity SIwave AC Solver or PSI AC Solver SIwave AC Solve Time = 15 min 7 sec Frequency Setup 1KHz <= f < 1GHz Genetic Algorithm Setup Optimized for Impedance Optimized for Total Number of Caps Optimized for Capacitor Types Optimized for Price Original solution Total # Caps: 74 Optimized Solution Total # Caps: 18 Capacitor Types = 5 AVX, Samsung, and Kemet 1.7nH 1.0nH.25nH ANSYS, Inc. February 2, 2018 ANSYS

31 PDN Transient Circuit Simulation The final step is to run a transient simulation to look at the Switching Power Noise Load Voltage Swing within 50 mv Target! Time-domain noise specification met ANSYS, Inc. February 2, 2018 ANSYS

32 Example : PCIe3.0 simulation Transient stimulus is applied to critical nets and the Near- and Far-Field response is computed in SIwave using Push Excitation. IBIS model is used for the controller to excite the TX, RX and CLK diff pairs 100MHz clock source (with jitter) for CLK PRBS7 for TX and RX; UI = 1ns (1/1GHz for PCIe3.0), 8b/10b encoding Terminate the pins at the Connector side using Resistors 100ohm differential termination Supply an ideal 1.5V input at the VRM node Connector Side (Termination) Controller Side (Driver) 1.5V supply clk_out Spectral Waveform Power supply lines ANSYS, Inc. February 2, 2018 ANSYS

33 EMI/EMC simulation : Near-Field Plots SIwave Near Field analysis is using the results from the transient simulation as current sources to excite the PCB with the true excitations (Push Excitation process) E 100MHz ANSYS, Inc. February 2, 2018 ANSYS

34 Thank you Merci ANSYS, Inc. February 2, 2018 ANSYS