Experience at INFN Padova on constrained PCB design Roberto Isocrate INFN-Padova

Transcription

1 Experience at INFN Padova on constrained PCB design Roberto Isocrate INFN-Padova

2 Experience at INFN Padova on constrained design 1. Why do we need Signal Integrity (SI) analysis (and constrained design)? 2. Design approach and Cadence tools 3. Agata GTS card description 4. Comparison between simulations and reality 5. Allegro SI 630 MGH short description 6. MGH simulations compared to reality

3 Why do we need SI and PI analysis? Die size decreasing Technology evolution Rise time becoming more rapid (bandwidth increasing) Lower power-supply voltage More current Critical length decreases Traces must be treated as transmission lines Less noise margin Impedance of power planes depends strongly on frequency

4 Technology Trend Decreasing Rise Time And Supply Voltage Increasing Number of Constrained Nets and Supply Current Technology

5 How Constrained Design Help designers? Logic Design Layout Allegro Design Entry HDL SI 610 Allegro PCB SI board Electrical Engineers SI Engineers Layout Designers ECSets

6 Typical design approach Logical Design System/Board Partitioning Up Front Concurrent Electrical/Physical Design Mechanical Design Pre- Layout Design Constrain Sets Constrain Driven PCB Layout And Verification Pre- Proto Sign-Off Prototype Fabrication and assembly Physical Hardware Verification Pre- Production Design Production Hardware

7 AGATA GTS Mezzanine card: short description Clock Generator isfp Transceiver Delay lines Jitter attenuator isfp Transceiver 2V5 Reg FLASH (boot) Mem Xilinx Virtex2Pro FPGA isfp Transceiver 1V5 Reg SDRAM SDRAM Memory Memory Mictor Mictor connectors connectors J1 J1 J2 J2 isfp Transceiver 10/100 Enet PHY

8 Brief description of Global Clock and Trigger distribution

9 AGATA GTS Mezzanine card short description isfp transceivers High speed cross-switch Clock generator FLASH Temp. sensor Tyco Mictor connectors Clock smoother FPGA Delay lines SDRAM

10 AGATA Global Trigger and Clock Distribution System The Team Marco Bellato (project leader) Luciano Berti Damiano Bortolato Roberto Isocrate Gabriele Rampazzo More info about AGATA AGATA web page

11 Cadence Allegro SI design approach Define specifications Simulation topologies Schematic entry Board debug Electrical and mechanical constrains, stackup, Post layout constrain evaluation Post layout SI verifications Board routing

12 Define specifications and Simulation Topologies

13 Models, Curves, Topologies

14 IBIS model sources The web : Google search Cadence libraries The supplier 3rd party custom

15 If you don t find a model Build it! Key ingredients: Pin List, I/O cell V-I curves, dv/dt, threshold voltages, etc. Embellishments: V-T curves, etc. Check run through parsers: IBIS: ibischk3 Cadence: ibis2signoise I/O cell source: Simulate from SPICE --> not likely & what s the point? Borrow something similar ********************************************************************* [IBIS Ver] 3.1 [File Name] rgl_1638.ibs [File Rev] 2.0 [Source] Borrowed and modified by RGL from a similar part HDMP_1636 also supplied by Agilent with the warning that the IO cells are somewhat different [Date] 6_12_00 ********************************************************************* (C) COPYRIGHT Com Corporation ********************************************************************* [Component] RGL_HDMP_1638 [Manufacturer] HP [Package] variable typ min max R_pkg.06ohms NA NA L_pkg 6.0nH NA NA C_pkg.5pF NA NA [Pin] signal_name model_name R_pin L_pin C_pin 1 GND_TXHS GND n.3p 2 TX0 Z530678_IN n.29p 3 TX1 Z530678_IN n.28p 4 TX2 Z530678_IN n.27p 5 TX3 Z530678_IN n.26p 6 TX4 Z530678_IN n.25p 7 TX5 Z530678_IN n.25p 8 TX6 Z530678_IN n.24p 9 TX7 Z530678_IN n.24p 10 TX8 Z530678_IN n.25p 11 TX9 Z530678_IN n.25p 12 NC NC 13 RXSEL Z530678_IN n.27p

16 Why IBIS? Advantages -Fast -Easy -Doesn t reveal proprietary information -Complete chip definition -Pin out - Cell Usage - AC and DC Specifications Disadvantages -IBIS model quality is generally poor -Accuracy can be an issue - Practical Issues and Limitations - Connectors/Package models - Different results from different simulators (portability) -IBIS committee slow to respond Advantages -Industry Standard - Berkley SPICE is Free - HSPICE has widespread acceptance -Accurate - Transistor levels models - Connectors, lossy transmission lines - if you can build it, you can model it Why SPICE? Disadvantages -Performance can be slow -Inconsistent net list formats and cryptic spice syntax

17 Schematic design entry

18 Define electrical constraints, stackup, mechanical constraints,

19 Board layout: place

20 and route

21 Post layout constraints evaluation

22 Example of propagation-delay equalization

23 Post layout SI verifications

24 Board debugging

25 Post layout topology extraction: examples #1

26 Post layout topology extraction: example #1

27 Post layout topology extraction: example #2

28 Post layout topology extraction: example #2

29 Post layout topology extraction: example #3

30 Post layout topology extraction: example #3

31 Post layout topology extraction: example #4

32 MGH design features System Analysis: Time domain simulations Loss Budgeting: S-parameters simulations High Capacity: Channel Analysis

33 Allegro PCB SI 630 Multi-GHz Technology There are two ways to simulate Tlsim Hspice

34 Wrap hspice model in dml 4 5 stimuli enable Need to map active device nodes to those shown Additional nodes can be used, these are simply the nodes the GUI interacts with 2 inputs 4 power pins Node 2 (and diff node 8) connect to interconnect for inputs, outputs, and IOs At the text level NOT TRIVIAL!

35 Hspice Wrapping Process Understand model to wrap Nodes, voltages, frequencies, etc Identify any related files (called, included or encrypted) Understand template Position of model subckt AND header info Header: model name, type, voltage, ramp, language, number of terminals Normal = 7-terminal, Differential = 8-terminal Worst case = BBox, (decision flow in Hspice Guide App. A) Paste model into template Fix header attributes Adapt nodes in model to nodes in template Test in simple circuit with SigXp calling Hspice and debug Find problems by searching for error in waveforms.lis Get more help at if needed

36 Post layout topology extraction of Gigabit lanes

37 Define stimulus

38 Run simulation It takes time! ~50minutes on 2 GHz Intel!!)

39 Gigabit lane simulation results

40 Gigabit lane simulation vs. measurements

41 MGH Analysis Loss budget Loss budget -13.8dB

42 MGH Analysis S-parameters Loss budget -13.8dB

43 Channel analysis Interconnect Storage Potential

44 It is very easy to introduce impedance discontinuities! Follow the rules!! Vias clearance! High speed differential vias Equalize the length difference between N and P signals Avoid stubs (if possible)

45 MGH analysis example how impedance discontinuities degrade the SI

46 Conclusions Constrained design offers an integrated high-speed design and analysis solution. Reading and writing to the same database avoid possible translation issues. SI analysis enables you to solve issues early in the design process. Due to the miniaturizations of components it is very complex to fix errors on prototypes Improved chances of first time success