Response Surface Channel Modeling Designer SI & DesignXplorer

Transcription

1 Response Surface Channel Modeling Designer SI & DesignXplorer 1 ANSYS, Inc. September 14,

2 Outline Product Introductions Designer SI DesignXplorer Intro to DOE & Response Surface Modeling Response Surfaces Sensitivity Plots Optimization/tradeoff Design simplification Defects Per Million Opportunities (DPMO) Summary 2 ANSYS, Inc. September 14,

3 Designer SI Circuit Simulator- Nexxim Engine (transient, fast convolution, statistical and IBIS-AMI circuit simulation) Integrated Schematic capture and layout tool Design 3 management ANSYS, Inc. September front-end 14, linking EM simulation products (HFSS, Q3D, SIwave,..)

4 Nexxim Circuit Engine Strengths Statistical analysis and transient simulation: New features VerifEye and QuickEye provide statistical analysis and fast convolution simulation capabilities. Time-domain simulation using frequency-domain S-parameters: Nexxim's inherent automatic enforcement of passivity and causality to accurately model and simulate physical behavior in the time domain (complex interconnects in signal integrity applications). To address the problem of passivity enforcement for large port count, non-passive S-parameter based models; "Passivity by Perturbation" option. Nexxim also includes the patented "TWA" algorithm. "TWA" will dramatically speed up the State Space fitting procedure often by orders of magnitude. State Space model generation is a critical need for time domain S-parameter simulation. Higher capacity at increased simulation speed: Cutting-edge numerical algorithms provide Nexxim with the capacity and speed to handle simulations of very large transistor/device counts, and high harmonic content without sacrificing simulation accuracy. Robust convergence: Nexxim includes robust algorithms across all analysis domains (DC, time and frequency) that ensure convergence even as circuit size, harmonic content and circuit nonlinearities increase. 4 ANSYS, Inc. September 14,

5 DesignXplorer DesignXplorer (DX) explores a wide range of responses from a limited number of actual solutions. It creates Response Surfaces Allows for optimization and six-sigma studies that include a large number of variations without requiring a simulation for all variations DX uses Design of Experiments (DOE) DOE method determines how many, and which design points should be solved for the most efficient approach to optimization Response surface is fit to solved DOE 6 ANSYS, Inc. September 14,

6 Why Response Surface Modeling? Response Surface Modeling enables the designer to model and consider all aspects of a high speed channel design. We fit a statistical model to outputs of the design as a function of the change in input variables. A DOE table is used to select design points to solve explicitly for and the statistical model so to speak, fills in the gaps Optimized conditions and worst case scenarios are obtainable within the set of all possible design combinations within a realistic simulation timeframe. For example consider 30 variables or factors, if each variable has only 5 variations or levels we are looking at a huge number of possible combinations in order to find optimal solutions and or worst case scenarios. Combinations Factors Levels 5 30!!!! 7 ANSYS, Inc. September 14,

7 PCIe Channel Example PCIe Gen 3 DOE Channel Simulation TX Package 1 Socket PCB Board Model PCI PCI Connector Board Package 2 RX ID=157 ID=156 ID=158 Pad Pad1_p Ball1_p Pad1_n Ball1_n Pad2_p Ball2_p Pad2_n Ball2_n Pad3_p Ball3_p Pad3_n Ball3_n Tline p1 p3 p5 p7 p9 p11 Ball Die_1p Die_1n Die_2p Die_2n Die_3p Die_3n Pin1 Pin2 Pin3 Pin4 Pin5 Pin6 Pin7 Pin8 Pin9 Pin10 Pin11 Pin12 Pin1 Pin2 Pin1 Pin2 Pin1 Pin2 Vias Pin3 Pin4 Pin3 Pin4 Pin3 Pin4 TLines Pin3 Pin4 Pin3 Pin4 Pin3 Pin4 Vias Pin1 Pin2 Pin1 Pin2 Pin1 Pin2 Pin1 Pin3 Pin5 Pin7 Pin9 Pin11 Pin2 Pin4 Pin6 Pin8 Pin10 Pin Die_1p Die_1n Die_2p Die_2n Die_3p Die_3n p1 p3 p5 p7 p9 p Ball1_p Ball1_n Ball2_p Ball2_n Ball3_p Ball3_n Pad1_p Pad1_n Pad2_p Pad2_n Pad3_p Pad3_n P2_Pad1_p P2_Pad1_n ID=187 ID=165 ID=164 P2_Pad2_p2 P2_Pad2_n2 W103 W176 W177 W P2_Pad3_n P2_Pad3_p 12 components consisting of multiple design parameters varying from material specific to physical. 8 ANSYS, Inc. September 14,

8 Example of model details Trace width and space Different dielectric regions for fiber skew Varying degrees of trace etching Varying dielectric materials Dielectric thickness Via stub lengths Routing configurations Via thickness Anti-pad sizes 9 ANSYS, Inc. September 14,

9 Problem Scale 30 different factors isn t unreasonable considering an entire PCIe Channel, Example: Package Thickness, Pad breakout, trace length, ball pitch, dielectric material (5) Socket Thickness, material properties, SG via ratio (3) Board MS and SL trace & space, etch factors, Cu roughness, dielectric materials, via config (8) Connector Various vendor models, often only one or two options. (1) 2 nd Board MS, SL, etch factors, Cu roughness, dielectric materials, via config (8) 2 nd Package Thickness, Pad breakout, trace length, ball pitch, dielectric material (5) 10 ANSYS, Inc. September 14,

10 DOE Workflow 11 ANSYS, Inc. September 14,

11 Circuit Simulation- HPC 12 ANSYS, Inc. September 14,

12 DOE Methodology 13 ANSYS, Inc. September 14,

13 PCIe Channel Example DOE Setup 14 ANSYS, Inc. September 14,

14 PCIe Channel Example DOE Setup 15 ANSYS, Inc. September 14,

15 Response Surfaces Visualize response surfaces in 3D or 2D plots (continuous, discreet, mixed) variables The Measure of fit provides a metric for evaluating the accuracy of the response surface model. 16 Eye Height Coefficient of Determination (R-Squared) = Eye Width Coefficient of Determination (R-Squared).= ANSYS, Inc. September 14, Provides a measure of how well future Outcomes will be predicted By the statistical model

16 Sensitivity Plots Which variables have the most impact on the output. Negative numbers show a decrease impact on output Positive numbers show an increase impact on output Sensitivity plots help us make the decision; which variable in my design offers the most impact changing my eye height or width. More importantly is shows up which inputs we may consider fixing thus narrowing the data set 17 ANSYS, Inc. September 14,

17 Optimization Min. EYE Height/Width 18 ANSYS, Inc. September 14,

18 Narrowing the field At this stage we know two valuable insights; which variable set yields the worst case eye which of those variables don t contribute much to this case. Additional judgment also comes into play here for example: Manufacturability Cost We narrow the field of variables and re-run the DOE for improved accuracy. Minimized to just the Package, Board, and Card T-line lengths 19 ANSYS, Inc. September 14,

19 Sensitivities updated of second DOE Package Length board Length Change in relative significance 20 ANSYS, Inc. September 14,

20 Defect Rate Prediction (DPMO) If we cannot achieve an acceptable design on one or more of our output criteria we need to determine whether or not our design can meet a specific defect rate target in this case, 1000ppm. For this case we will leave the design in the worst case and see how it does in the six sigma analysis for DPMO (Defects Per Million Opportunities) or ppm ( parts per million) 21 ANSYS, Inc. September 14,

21 6-Sigma Distribution functions Plots showing the normal probability distribution and Cumulative distribution functions for Eye Width and Eye Height. 22 ANSYS, Inc. September 14,

22 Distribution Characteristics 23 ANSYS, Inc. September 14,

23 DPMO Eye Height at worst case is with in the PCIe spec at 25mVPP Eye Width simulation shows possible violations of 0.3(UI) with a Sigma Level of With a Sigma Level at corresponding to 559 DPMO were within our 1000DPMO goal!! 24 ANSYS, Inc. September 14,

24 Summary Response Surface Modeling enables the designer to model and consider all aspects of a high speed channel design. optimized conditions and worst case scenarios are obtainable within the set of all possible design combinations within a realistic simulation timeframe. Using a cohesive tool set such as Designer SI and DesignXplorer improves simulation time, and reduces operator error. Designer Si as the circuit simulation tool directly linked to electromagnetic models yields the highest possible accuracy. Transient, statistical transient, peak distortion analysis, and equalization schemes are all inclusive within the Designer environments and can be part of the DOE, improves goodness of fit R^2 25 ANSYS, Inc. September 14,

25 Summary of tools Designer SI Circuit HFSS SOD DesignXplorer HPC pack 26 ANSYS, Inc. September 14,