Power integrity is more than decoupling capacitors The Power Integrity Ecosystem. Keysight HSD Seminar Mastering SI & PI Design

Transcription

1 Power integrity is more than decoupling capacitors The Power Integrity Ecosystem Keysight HSD Seminar Mastering SI & PI Design

2 Signal Integrity Power Integrity SI and PI Eco-System Keysight Technologies 2017 Page 2

3 What Does the Power Distribution Network Look Like? The Real World PDN Network Package Pkg Device Device Detail Supply Noise Ground Noise Keysight Technologies 2017 Page 3

4 Is Target Impedance Really this Simple? Z Target Target Impedance Calculation ( Power _ Supply _ Voltage) ( Allowed _ Ripple) Current Example: 4 A 3.3 V 2 A VRM 3.3 V Power Plane Z Target V I (3.3V ) (5%) ZTarget(3.3V) 82. 5m 2A Target Impedance is the goal that designers should hit!!! Keysight Technologies 2017 Page 4

5 L-C Series Resonance Problem with Capacitors Keysight Technologies 2017 Page 5

6 L/C Parallel Resonance Problem in the PDN Design Keysight Technologies 2017 Page 6

7 IMPEDANCE (OHMS) Power Delivery Target Impedance Flat Z at lower frequencies reduces the package/ DUT anti-resonance at higher frequencies! VRM Impedance Decoupling Sink Interconnect FREQUENCY (Hz) Keysight Technologies 2017 Page 7

8 Forced and Natural Response Time Domain Kick Droop Power Rail Natural Forced Current Load Keysight Technologies 2017 Page 8

9 Spectral Content of the Sink Digital Switching Spectral Content PRBS Edge speeds determine the di/dt maximum for Ldi/dt ripple voltage. I(t) waveform determines the spectral content, digital patterns have a wide bandwidth (peaks are at odd harmonics of clock rate) SINE Keysight Technologies 2017 Page 9

10 Z is below target, but not flat.. Is this a problem? Z Target Keysight Technologies 2017 Page 10

11 How to Design for Power Integrity: Finding Power Delivery Noise Problems Steve Sandler Picotest Author of Power Integrity Keysight Technologies 2017 Page 11

12 Start at the Voltage Regulator Module to Design for Flat PDN Minimizes the quantity of capacitors to reach target Z DeCap1 DeCap2 C = L slope 2 Z desired No DeCaps vs. With DeCaps 2 Z desired L slope Page 12

13 How to get a flat VRM Impedance Page 13

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18 1-Port Reflect vs 2-Port Shunt Through Page 18

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20 Separating PCB Mounting L from C ESL Page 20

21 Manufacturer s Demo PCB Not Flat, Hard to Measure Page 21

22 VRM Characterization Board for Flat Z Design Page 22

23 Measured Models How to Video Page 23

24 State Space Hybrid Model LM20143 Switching Transients & Small Signal Impedance Page 24

25 Modern Day PCB s Have Increasing Data Speed and Complexity Xilinx KCU105 FPGA Kit HDMI : 2.0 = 6Gbps 3.1 =10Gbps FMC : 2Gbps ~ 10 Gbps DDR4: 3.2Gbps USB3.0: 5Gbps 3.1 =10 Gbps SFP: 8Gbps 16Gbps w 64b/66n encoding, QSFP 25 Gbps+ PCI-E : 3.0 = 8 Gbps 4.0 = 16Gbps 9.27 x 5 inch, 16 layers PCB Page 25

26 Modern Applications with Multiple PDNs Xilinx Kintex VCU105 Board: Power Planes 15 Major Power Distribution Networks (PDN) 16 Layer PCB Page 26

27 PIPro DC IR Drop Sink : U V Vdrop= 53 mv Sink : U V Vdrop= 52 mv Voltage and current reported per Via, Sink, VRM and more! VRM: U4 1.2 V Power Dissipation and Current Density visualization Sink : U V Vdrop= 52 mv Sink : U V Vdrop= 52 mv Xilinx KCU105 VCC1V2 PDN Page 27

28 EM Simulations for Multi-Port PDN PCB Models 64 Port PDN PCB EM Circuit Model (S-parameter Behavioral Model) No Capacitors Z frequency With Capacitors Z ADS PIPro and SIPro frequency Page 28

29 PIPro AC PDN Impedance Analysis Voltage, current and Power Loss Density Plots Component Model assignment: Lumped SnP Murata Samsung TDK Create custom parts from Schematic models Easy setup: Filter, drag and Drop Components + Full scripting support for setup, simulation and post-processing Page 30

30 PIPro AC PDN Impedance Analysis Decoupling Capacitor Selection in PIPro Voltage, current and Power Loss Density Plots Analyze effect of decap model changes without any need to re-simulate Original PDN Impedance New Model Selected Page 31

31 One Group of Decaps Decaps PIPro AC PDN Impedance Analysis Decoupling capacitor tuning from schematic Top-level Model VRM Choke VRM Memory-1 Memory-2 Memory-3 Memory-4 Controller From PIPro PCB Model Values Tuning Completely flexible PDN optimization strategy Page 32

32 SI and PI Co-EM Simulation Power and Signal Nets in the same EM simulation Page 33

33 Vendor Specific IBIS Models to Improve Accuracy Xilinx Kintex FPGA and Micron DDR4 IBIS models Kintex IBIS Micron IBIS Page 34

34 Simultaneous Switching Noise (SSN) VCCO Pin Noise Voltage By SSON Shows SSN noise voltage at VCCO pin, which is similar to the measured data Both eye width and height are reduced by SSO noise, as expected p 375p, 510mV 474mV respectively No PDN Ideal VCCO With SSON Page 35

35 SSO Noise Measured Example Simultaneous Switching Output Noise (SSON) CLK DQs DQ VCCO SSO Noise Page 36

36 SI with PI, PI with SI, and SI PI Co-Simulation Loss, Delay, Crosstalk S-Parameters EEsof ADS SIPro and PIPro Integrated EM Simulation IR Drop, AC Impedance EM Behavioral Model S-Parameters SI PI SI and PI Page 37

37 Want More Resources? ADS Bundle Used for Power Integrity Analysis: W2222BP Power Integrity Bundle: ADS Core, TransConv, Harmonic Balance, Layout, PIPro Signal Integrity & Power Integrity Resources Try it for free for 30 days with absolutely no obligation. Page

38 Thank You! Page 39