Controlled Impedance Line Designer

Transcription

1 Heidi Barnes WW HSD Application Engineer Controlled Impedance Line Designer Stephen Slater HSD Product Manager EDA Simulation Tools for Power Integrity

2 Agenda 1. Designing a channel for a desired impedance 2. What insights can the substrate stackup give us, to improve our channel design for the metrics that matter? 3. Demonstrating Controlled Impedance Line Designer, and new S- parameter tools in ADS 4. Where to find more information and test drive the tool! Power Integrity Page 2

3 Designing a Channel for a Desired Impedance Where to begin? A Transmission Line Calculator As Fabricated Model Refinement Process EM Simulation Input Data to Substrate Definition Input Data to EM Substrate Definition Multilayer Line Parts Ready for simulation Powerful Optimization! Power Integrity Page 3

4 Introducing A New Approach A productive flow to reach an Optimum PCB Stackup Design Import from Enterprise Layout Create New from Template One Substrate Stack-Up Definition EM Simulation of Layout CILD Refine Substrate and T-Lines T-Lines used in Pre-Layout Simulation Generate Layout and perform EM Verification Adjust T-Lines to get excellent agreement with As Fabricated measurement results Power Integrity Page 4

5 Agenda 1. Designing a channel for a desired impedance 2. What insights can the substrate stackup give us, to improve our channel design for the metrics that matter? 3. Demonstrating Controlled Impedance Line Designer, and new S- parameter tools in ADS 4. Where to find more information and test drive the tool! Power Integrity Page 5

6 Deeper Insights: Controlled Impedance Line Designer - Microstrip Single-Ended - Microstrip Edge-Coupled - Microstrip Broadside-Coupled - Stripline Single-Ended - Stripline Edge-Coupled - Stripline Broadside-Coupled - Coplanar Waveguide Single-Ended - Coplanar Waveguide Edge-Coupled Power Integrity Page 6

7 Which variables impact PCB Channel Loss the most? My Application Length = 40mm LossTan=.006 Width=0.3 mm Cu = 5.6e7 S dk = 3.6 Worst Case vs Length 100mm to 25mm Stop 25 mm Start 100 mm Worst Case vs Loss Tangent 0.02 to Stop Start 0.02 Worst Case vs Width 0.1mm to 0.5mm Worst Case vs Conductivity 1e7 S/m to 1e8 S/m Worst Case vs dk 3.0 to 4.4 Stop 0.5mm Stop 1e8 S/m Stop mm Start 1e7 S/m Start 4.4 Worst Case: 100mm Length, 0.02 LossTan, 0.1mm Width, 1e7 S/M, 4.4 dk Power Integrity Page 7

8 Using CILD to model Real World PCB T-lines Complicated stackup, loss, trapezoidal, frequency-dependent parameters Z = R + jωl G + jωc Finite R and G Skin depth Conductor roughness Dielectric loss tangent Power Integrity Page 8

9 Deeper Insights: Not Just Impedance Traditional Plots: Y-axis: Zc, Attenuation, Delay, and Effective e r Top row: X-axis is frequency sweep, family of curves for various swept widths Bottom row: X-axis is width sweep, family of curves for various swept frequencies Power Integrity Page 9

10 What do we do with the insights from CILD? Constant balance of conflicting design requirements, e.g.: Can I get away with less copper thickness? (save money, more loss) Real estate on the board is at a premium, can I adjust the Thickness of the dielectric to achieve my design goals. (How does it affect the spacing requirement?) Use CILD to set design rules to get what you want. Use statistical sweep to understand the sensitivities. The Fabricator will dial in the process to match your requirements, but you ve already insured the performance you expect. Power Integrity Page 10

11 When Finished Export a Line Type Definition Stored in ADS library to be used in - Schematic - Layout Cross Section info - Layers of signal lines and planes - Width(s), spacing(s), clearance(s), number of parallel lines Power Integrity Page 11

12 Line Type Components and Traces For Schematic and Layout Use Layer information from Line Type Width, Spacing and Corner Style either taken from Line Type or from a component s parameter Power Integrity Page 12

13 Fast Re-Optimization of EQ For Each Candidate T-Line Designing for the Metrics that Matter Power Integrity Page 13

14 Sweep T-line Parameters for Best Post-EQ Eye Designing for the Metrics That Matter! Power Integrity Page 14

15 Measurements Correlation at 40 GHz EM MODEL T-LINE MODEL 1.5 inches, 10mil width, 342 mil Stub MEASURE CMP28 Starter Kit Power Integrity Page 15

16 Fast Measurement-Based Models - refining T-Lines created from CILD Start with Design Parameters Fine Tune starting with Er Long Transmission Line Structure Series Resonant Beatty Structure Power Integrity Page 16

17 Agenda 1. Designing a channel for a desired impedance 2. What insights can the substrate stackup give us, to improve our channel design for the metrics that matter? 3. Demonstrating Controlled Impedance Line Designer, and new S- parameter tools in ADS 4. Where to find more information and Test drive the tool! Power Integrity Page 17

18 Demo Stub Resonator Example Stripline Stub Resonator Test Structure CILD Line-Type Model with Embedded Fixture Measurement vs. Simulation in ADS CMP-28 Stripline Resonator 10 Gb/s, PRBS 9 SIMULATED MEASURED N4951A Pattern Generator Power Integrity Page 18

19 Take Action! Try it for yourself Download this presentation and try out the demos at: Contact your Keysight representative for licensing and questions Power Integrity Page 19