Design and Simulation Tools for RF, Power and Signal Integrity. Pratik Khurana EEsof EDA Keysight Technologies

Transcription

1 Design and Simulation Tools for RF, Power and Signal Integrity Pratik Khurana EEsof EDA Keysight Technologies

2 Why Simulation? What is the Value? Without Simulation: Learn from Try and Error Simulation allow the user to observe the impact of their choices without the outcome having any impact on the real operation and predicts the functionality Page 2

3 Electronic Design Automation (EDA) IDEA CONCEPT DESIGN PRODUCT Page 3

4 Keysight EEsof EDA : Design flow Proposal System, Analog, HSD, RF/MW, EM, EMI/EMC Analysis and integration with third party tools up to final Test System simulation: Baseband, RF/MW Communication systems, Radar Circuit simulation: Analog, Signal Integrity, RF/MW Physical Design: Layout Verification & Test Page 4 Physical analysis: EM, SI/PI, EMI/EMC & Electro-Thermal Simulation

5 Converting Concept to Product Packaging, Antenna RF Board Integration RFIC Design & Module System Concept Page 5 Final Product

6 Converting Concept to Product Keysight EDA Software help Packaging, Antenna RF Board Integration RFIC Design & Module System Concept Page 6 Final Product

7 Outline System Level Electronic Design with SystemVue RF Board Design with ADS, EMPro and Genesys Impedance Matching Application PCB Signal Integrity & Power Integrity consideration with ADS, SIPro and PIPro Signal Integrity Power Integrity Page7

8 What is SystemVue? System-level design cockpit, focused on Communications #1 SystemVue models Physical Layer (PHY) architectures across multiple Baseband & RF domains, for better system designs #2 SystemVue provides an implementation path to FPGA/DSP hardware #3 SystemVue enables cross-domain verification, connecting Baseband algorithm to RF tools, Standards references, and Test & Measurement. Page

9 Validate Comms before/after R&D commitments Transition naturally from Design Test with a single cockpit IP Reference Libraries 4G LTE-Advanced, LTE STANDARDS 3G HSPA+, WCDMA, etc WLAN ac/n/a/ REFERENCES WPAN ad, c RF / Analog Channel Modeling BB Algorithm Modeling BASEBAND MATLAB.m FixedPoint, HDL/FPGA MODELING Embedded C++ RF SYSTEM MODELING MIMO Channel (OTA) Digital Pre-Distortion (DPD) RF System Design RF EDA platforms Filtering, EQ, Modem Test Software Test Equipment RF TO Sources & Analyzers LINKS AWG & Digitizers REAL WORLD, Scopes, Logic, Modular HARDWARE TEST I/O Lib, ComExpert VSA Signal Studio 3rd Party Page 9

10 Validate Comms before/after R&D commitments Transition naturally from Design Test with a single cockpit IP Reference Libraries Quickly capture system level design concepts Model implementation-level impairments 4G LTE-Advanced, LTE 3G HSPA+, WCDMA, EDGE, GSM WLAN ac/n/a/b/g WPAN ad, c RF / Analog Channel Modeling BB Algorithm Modeling MIMO Channel (OTA) Digital Pre-Distortion (DPD) RF System Design RF EDA platforms MATLAB.m FixedPoint, HDL/FPGA Embedded C++ Filtering, EQ, Modem Test Software I/O Lib, ComExpert VSA Signal Studio 3rd Party Test Equipment RF Sources & Analyzers AWG & Digitizers Scopes, Logic, Modular Connect BB, RF, and T&M for rapid validation Rapid prototyping with integrated measurement Page 10

11 Who uses SystemVue? System Architects Simple and easy model based design workflow Multi-domain modeling for RF, baseband, and algorithms Fast link level analysis of Layer 1 systems Baseband Architects & Algorithm Developers Typical Design Organization Multi-language Modeling Target Neutral IP development Cross domain debugging of IP RF System Architects Accurate models and analysis in native Frequency domain Flow integrity with circuit level design (ADS) Integration with vector modulation analysis Embedded FPGA and DSP HW Designers Advanced analysis and heuristics for fixed point systems Link algorithms to HW in common formats Structured verification from design to implementation System Verifiers Use measurement-grade reference IP, or create custom signals Verify system block level interoperability at all levels of H/W abstraction IP aggregation, including both BB and RF Systems Page

12 MATLAB Script, for in-line algorithm modeling Familiar use model, without leaving SystemVue MATLAB Script 100% consistent with retail MATLAB 1-click toggle to switch to your own locally licensed MATLAB Leverage your libraries and toolboxes from within SystemVue WORK SPACE TREE WORK SPACE VARS Included with base W1461 SystemVue environment COMMAND PROMPT Page

13 SystemVue FPGA Design Flow SYSTEM LEVEL POLYMORPHIC MODEL FIXED POINT Co-sim Wrapper VHDL/Verilog File Hierarchy VHDL/Verilog File Hierarchy Aldec Riviera-PRO RTL FPGA Co-sim Wrapper Altera Quartus II Xilinx ISE IP, Place & Route, Synthesis IP, Place & Route, Synthesis Stratix IV/V Cyclone IV Virtex Mentor ModelSim Riviera-PRO HDL simulation ModelSim HDL simulation UI, Libraries Simulation Visualization Debugger UI, Libraries Simulation Visualization Debugger Hardware in-the-loop (HIL) Page 13

14 SystemVue Demo 14

15 Result: An integrated, tops-down design flow Cross-domain model-based design: RF, Comms, and C++/HDL MEASUREMENT, ANALYSIS Algorithms C++,.m System design RF Architecture Baseband design PHY Reference Dataflow Simulation FlexDCA software VSA software.m/c++ ALGORITHM Handwritten HDL Custom IP HDL Simulator(s) Target-neutral HDL Generation FPGA Synthesis Infiniium Scope.bit Files MXA / PXA SIMULATED H/W FPGA Target Logic Analyzer Wideband AWG REAL HARDWARE MXG / ESG RF sensor DIGITAL BITS, or MODULATED CARRIERS Page15

16 Outline System Level Electronic Design with SystemVue RF Board Design with ADS, EMPro and Genesys Impedance Matching Application PCB Signal Integrity & Power Integrity consideration with ADS, SIPro and PIPro Signal Integrity Power Integrity Page16

17 RF Board Design Front-end & Back-end design with ADS Schematic entry & simulation Tuning, Optimisation, Monte Carlo Layout editing 3D Electromagnetic Co-simulation Page 17

18 ADS - Advanced Design System Premier High-Frequency & High-Speed Design Platform Schematic Entry RF Layout and Verification Data Display and Post Processing Industry leading simulation technology Tuning/Optimization & Statistical design 3D planar & full 3D EM field solvers Best and broadest selection of Foundry developed PDKs & SMD libraries Design Flow Integration with Cadence, Mentor, Zuken, Intercept, X-parameter model generation from circuit schematic and Keysight's NVNA Wireless Libraries enable design and verification of designs to emerging wireless standards ADS helps designers fully characterize, optimize and produce designs. Page 18

19 Front End Design Simulation Frequency Industry leading simulation technology to enable first-pass design success. SpectraSys AC SParameters Harmonic Balance Physical What IF Transient Numeric Time Convolution Circuit Envelope Channel Ptolemy Timed Dataflow System Multi-Layer Interconnect Library Momentum Advanced Model Composer FEM Capabilities X-Parameter Simulation and Model Generation Keysight EEsof EDA Page 19

20 ADS & EMPro RF Design Environment ADS Platform EMPro Environment Electromagnetic Co-simulation AMDS EMDS Momentum Simulator Method of Moments FEM Simulator FDTD Simulator Finite Element Method Finite Difference Time Domain Page 20

21 EMPro ADS Common Database Integration improves your productivity. Common Database ADS Layout (3D View) EMPro 3D Design ADS Schematic EMPro projects now saved as ADS libraries 3D models now directly available in ADS as schematic and layout views Changes made in EMPro dynamically update in ADS Parameters created in EMPro available in ADS for EM sweep/optimization Page 21

22 EMPro 3D EM Modeling Environment Interactive, Intuitive, Efficient, 3DEM design Environment Full Wave 3D EM FEM and FDTD Simulation Technologies Parameterize 3D EM components for co-simulation & optimization in ADS Transfer ADS Layouts to EMPro for additional 3D-EM simulation Full scripting (Python) and parameterization capability Windows & Linux Page

23 Advanced 3D Modeling Tools Chamfer Edges Revolve Blend Edges Draft By Angle Twist Loft Faces Draft By Law Hole w/wo Draft Page Shell Hole Special 23

24 Geometry Building Blocks Quickly create common shapes Easily parameterized and modified from the standard parts tree Page 24

25 Material Definitions and Assignments Use materials from the default library, or create your own Simply drag and drop material definitions onto parts Support for complex permittivity materials Default Library Page 25

26 Importing CAD Files in EMPro EMPro allows import of various industry standard CAD formats Supported CAD formats Page 26

27 Impedance Matching Application Page 27

28 Designing with Off-The-Shelf components For IoT Impedance Matching for Sub 1GHz Frequency (Sub 1 GHz) and Narrow Bandwidth (200 khz), e.g. ZigBee, SIGFOX, LoRa, Weightless Matching Chipset to Antenna Chipset Impedance Matching Antenna IoT Module Customizable in Footer Page 28

29 Designing with Off-The-Shelf components For IoT Impedance Matching for Frequency (2.4 GHz) and Broader Bandwidth (20MHz) Matching Chipset to Amplifier to Antenna Chipset Impedance Matching Amplifier Impedance Matching IoT Module Antenna Customizable in Footer Page 29

30 Impedance Matching Network Design Increasing Levels of Difficulty 1-Stage Matching Network Zsource 2-Stage Input Matching Network Zload Output Matching Network Zsource Zload 3-Stage Antenna Input Matching Network Interstage Matching Network Output Matching Network Page 30 Zload

31 Automatic Impedance Matching Synthesis Quickly design impedance matching for economic and practical implementation 1. Define Freq and BW to do Impedance Match 2. Browse to S-, X or Sysparameters of Chip, Amplifier and Antenna that needs matching 3. Select matching topologysimpler is cheaper to realize 4. Matching networks synthesized in seconds 5. Quality of match is automatically optimized 6. Experiment with lumnped / distributed matching for economy 31 IMS 2016 MicroApps Page

32 A New cohesive flow for Signal & Power Integrity

33 Outline System Level Electronic Design with SystemVue RF Board Design with ADS, EMPro and Genesys Impedance Matching Application PCB Signal Integrity & Power Integrity consideration with ADS, SIPro and PIPro Signal Integrity Power Integrity Page33

34 ADS: SIPro and PIPro A Cohesive Workflow for SI and PI Analyses Layout Import into ADS (Direct *.brd Import, Allegro ADFI or ODB++ flow) Transient Convolution Channel Sim DDR Bus Sim SIPro / PIPro Analysis Layout ADS Schematic Set up and run analyses Manage nets, VRMs, sinks, components 3D layout view and results visualization 4 New EM Simulators PI-DC IR Drop PI-AC PDN Impedance Power Plane Resonances Power-Aware Signal Integrity Page 34

35 Increased Productivity for Post-layout Analysis Seamless flow from EM-analyses back into schematic for both SI and PI Decap Tuning, Optimization, Circuit-level VRM modeling Channel simulation and Transient simulation I/O ports Automated Test Bench Generation SSN Analysis Automated Sub-circuit Generation Data with VCC Bounce DDR4 Low BER Simulation PDN Impedance Compliance Test S-parameter Extraction Page 35 And More Simulation!

36 Outline System Level Electronic Design with SystemVue RF Board Design with ADS, EMPro and Genesys Impedance Matching Application PCB Signal Integrity & Power Integrity consideration with ADS, SIPro and PIPro Signal Integrity Power Integrity Page36

37 SIPro Simulation Technology Overview A composite technology of fast FEM + Planar EM Speed and Accuracy Power-Aware Signal Integrity A purely EM-based simulation, capturing more EM effects than 2D-hybrid solutions SI-specific, net-driven use-model and flow Easily plot Transmission, Return loss, Xtalk and TDR/TDT Automatic-schematic generation EM model flows back to schematic ready for further simulation with Transient, Channel Sim, DDR Bus Sim and more Power-Aware Signal Integrity 6/3/2016 Page 37

38 SIPro: Speed and Accuracy Xilinx KCU105 FPGA Platform Board Example : SFP (Small Form Factor Pluggable) TX channel Very good agreement! SIPro finished in 18 min, a fraction of simulation time compared to FEM SIPro: 1GB memory, 6 secs per frequency point FEM:8GB memory, 12 mins per point Customizable in Footer Page 38

39 SIPro: Accuracy DDR4 DQ Channel, Measured vs SIPro Measurement: Courtesy of GigaTest Labs 28-layer Xilinx UC1650B DDR4 memory characterization board DDR4_C2_DQ4 single ended line (cookie cut) DDR4_C2_DQ4, Single Ended 2431 mil path length 20GHz or 2λ with Er=4) Er as specified by the designer, not as fabricated Red = SIPro Black = Measured Customizable in Footer Page 39

40 SIPro: SI-specific use-model and flow Layout to results in less than 20 clicks No layout simplification required! Net-driven Guided port creation Quickly plot all crosstalk elements from the same component Easily plot TDR/TDT Mixed-mode S-parameters 6/3/2016 Page 40

41 Outline System Level Electronic Design with SystemVue RF Board Design with ADS, EMPro and Genesys Impedance Matching Application PCB Signal Integrity & Power Integrity consideration with ADS, SIPro and PIPro Signal Integrity Power Integrity Page41

42 The Power Distribution Network Why doing a PDN analysis? VRM Sinks 1.2V Power Rail 1.189V Ground Rail 0.002V Roles of the PDN (Source: Signal and Power Integrity Simplified, Second Edition, Eric Bogatin) Keep a constant supply voltage on the pads of the chips, from DC up to the bandwidth of the switching current. Carry the return currents for the signal lines and avoid these overlap. The latter causes ground bounce or simultaneous switching noise (SSN). Seen the PDN has the largest size, carries the highest currents including HF noise, it has the potential of creating most radiated emissions. HSD2 - PIPro Hands-on Page 42

43 PIPro Simulation Technology Overview PIPro has an efficient net-driven PI analysis setup with 3 new simulator engines Speed and Accuracy PI-specific net-driven use-model and flow Change decap values/models without needing to re-simulate Automatic-schematic generation EM model flows back to schematic ready for further simulation with behavioral and circuitlevel simulations of VRMs, sinks and more PI-DC IR Drop Power Plane Resonances PI-AC PDN Impedance 6/3/2016 HSD4 Page 43

44 PIPro: Accuracy Customer validated test-case, Simulation vs. Measured Data Bare-Board PDN populated with Decaps measurement PIPro PiPro measurement PIPro PiPro 1 0 Z11 [Ohm] Z11 [Ohm] Customer used ideal cap values with no ESR specified, hence sharp resonances Frequency [GHz] Test case: ATE test card PDN traverses many layers Frequency [GHz] Ideal VRM model. Customer did not have IC data. 6/3/2016 HSD4 Page

45 Designed for Usability Filter by Net Filters Filter by Component Context sensitive menus Right-click to add-toanalysis Drag & Drop Hierarchical search for complex selections Easily copy setups from one analysis to another Context sensitive menus e.g. Select instances connected to ONLY the selected nets 3D Layout View Color coded Nets 6/3/2016 HSD4 Page 45

46 PIPro DC IR Drop Sink : U V Vdrop= 53 mv Sink : U V Vdrop= 52 mv Voltage and current reported per Via, Sink, VRM and more! VRM: U4 1.2 V Sink : U V Vdrop= 52 mv Sink : U V Vdrop= 52 mv Xilinx KCU105 VCC1V2 PDN Page Power Dissipation and Current Density visualization

47 PIPro AC PDN Impedance Analysis Voltage, current and Power Loss Density Plots Component Model assignment: Lumped SnP Murata Samsung TDK Create custom parts from Schematic models Easy setup: Filter, drag and Drop Components + Full scripting support for setup, simulation and post-processing Page 47

48 PIPro AC PDN Impedance Analysis Decap Selection in PIPro Voltage, current and Power Loss Density Plots Analyze effect of decap model changes without any need to re-simulate Original PDN Impedance New Model Selected Page 48

49 PIPro AC PDN Impedance Analysis Decap tuning from schematic Top-level Model VRM Choke VRM Memory-1 Memory-3 Memory-4 Decaps Memory-2 Controller Values Tuning From PIPro Completely flexible PDN optimization strategy One Group of Decaps PCB Model Page 49

50 PIPro Power Plane Resonance Analysis Self resonances Analyze self-resonances of the PCB and inspect trouble areas that have the highest field strength Page 50

51 Keysight EEsof EDA Your software partner for IoT development Packaging, Antenna RF Board Integration RFIC Design & Module System Concept Page 51 Final Product