Using GoldenGate to Verify and Improve Your Designs Using Real Signals

Transcription

1 Using GoldenGate to Verify and Improve Your Designs Using Real Signals Enabling more complete understanding of your designs Agilent EEsof EDA 1

2 Outline What problems do designers face? Main point of this presentation What does GoldenGate enable you to do? Ways GoldenGate simulates modulated signals Examples Summary 2

3 What problems do designers face? Will my design meet specifications? What part of my design is causing the biggest degradation? Does varying a parameter improve performance? If so, which parameter and how much? 3

4 Main point of this presentation RFIC designs are under-characterized One- or two-tone simulations are useful, but not sufficient Need modulated signals for better understanding, more complete verification 4

5 What does GoldenGate enable you to do? Simulate modulated signals from Ptolemy or files, with correct characteristics bandwidth, peak-to-average power ratio, etc. Include interfering signals View specification-compliant results View performances at different points in your design Run simple simulations, quickly, for design investigation 5

6 Ways GoldenGate simulates modulated signals Virtual Test Benches Easiest if simulating WLAN a, b (WiFi), WMAN e (WiMax), TDSCDMA, or 3GPPFDD (WCDMA) Export sources and sinks from Agilent Ptolemy Numerous signals available 3GPP LTE, UWB, GSM, EDGE, DTV, etc. From.txt,.sig,.ascsig, or.wfm files. May be created with Agilent Signal Studio Generic modulated signals (QPSK, OQPSK, or pi/4 DQPSK) from the ENVELOPE source library in gglib 6

7 Advantages and disadvantages of each method Virtual Test Benches Easy setup, specification-compliant, results displayed automatically. Requires Ptolemy license. Exported sources and sinks Great flexibility, specificationcompliant. May need Agilent help to create, requires Ptolemy license. From file no license needed, but may only change carrier frequency and signal amplitude, limited post-processing. Generic modulated signals no license needed, but may not be specification compliant, limited post-processing. 7

8 Examples Power amplifier with WLAN signal LNA degradation due to noise, blocker Power amplifier with LTE signal Raw EVM and specification-compliant EVM of baseband chain Raw EVM of receiver (a predictor of BER) Raw EVM of transmitter versus variable gain amplifier gain setting 8

9 Power amplifier with WLAN signal (1) Simulation test bench Power amplifier subcircuit Spirals modeled using Momentum 9

10 How does Momentum help you in RFIC design? Create more accurate models than those in your PDK Create models for structures or components not in your PDK Check coupling effects due to adjacent structures in layout Use directly within the Cadence Virtuoso layout environment Integrate results with extracted parasitics from rest of layout Visualize current flow 10

11 Momentum capabilities and features Full-wave electromagnetic solver based on Method of Moments gives full dispersion and radiation Quasi-static EM solver for faster modeling of larger designs (more layout structures but small compared to wavelength) Fully integrated in Cadence Virtuoso layout environment Very efficient swept frequency analysis Includes sidewall coupling between thick metal traces Automated multi-threading dramatically speeds simulations when multiple CPUs available Comprehensive data display for viewing and post processing results 11

12 Example of multiple, coupled spirals Multiple spirals, including coupling Use S-parameter results in other simulations 5 minutes 10 secs. to simulate 0-50 GHz using 8 CPUs, via multithreading. 734 Mbytes. 12

13 Using Momentum components with Cadence Assura extraction tool Momentum component must be created without a reference pin Assura rules file (extract.rul) must be modified to define pinlayers and the geomconnect rule Momentum component must be defined as a blackbox to ensure the blackbox cell is extracted and keeps connectivity with the rest of the circuit 13

14 Overview of Momentum use model assuming what you want to simulate is already a cell Make Virtuoso cell a Momentum cell Simplify via arrays Define substrate stack up if not supplied in PDK Assign ports to pins in layout Check and/or set simulation options Run the simulation Automatically generate a model that may be used in other simulations 14

15 Will simulate spiral inductor from RFIC VCO VCO spiral inductor layout view 15

16 Create Momentum view from layout view (1) Select Tools> Momentum Creates Momentum-Virtuoso menu 16

17 Via arrays in momentum view should be simplified Via arrays 17

18 Simplifying via arrays flatten layout Select component and flatten it so it may be edited Select these options After executing, should be able to select individual via elements 18

19 Perform via simplification Select Pre-Processing > Perform Via Simplification These settings work well for this design Via arrays after simplification 19

20 Specify substrate file *.tch files define stack up in text file. *.ltd files may be used in Substrate Editor GUI. Use Substrate Editor to see or modify substrate materials or stack up 20

21 Define simulation frequencies Dots: actually simulated points Trace: calculated response Adaptive frequency sampling minimizes number of points required to accurately characterize frequency response. May add specified frequency points, also. 21

22 Define ports Auto-generate is easiest method One port is assigned to each pin in the layout 22

23 Specify simulation options RF mode should be faster if layout is electrically small. 3D-distributed includes horizontal sidewall currents Using Edge Mesh improves accuracy slightly, but problem size becomes much larger 2D-distributed used for vias because original via arrays would not have significant horizontal sidewall currents Recommended for relatively thick traces close to each other 23

24 Run simulation Substrate only has to be computed once Layout is electrically small below 429 GHz Multi-threading speeds up simulation automatically detects 8 CPUs 24

25 Simulation results Dots: actually simulated points Traces: responses calculated from Adaptive Frequency Sampling algorithm 25

26 Create simulator views to re-use results Creates symbol without reference pin Creates symbol(s) with and/or without reference pin New views created Symbol view inserted in a schematic 26

27 Computing L, R, and Q from the Momentum S- parameter model This is the simplest equivalent circuit model for computing Q. L R Q 27

28 Page 28 JivaroGG Key Features

29 Jivaro for GoldenGate What does it do? Jivaro for GG is a model (RC parasitics netlist) order reduction tool based on several different algorithms that reduce the order while keeping the accuracy within specified tolerances. Includes error control, that supervises the accuracy of the different algorithms. The default is very conservative leading to very accurate reduction up to highest frequencies. The default accuracy can easily be degraded by the user in order to gain higher reduction rate. Goals are: Get the same simulation results, but: Smaller memory footprint for GoldenGate simulation Enhance already best in class speed of GoldenGate Allows the maximum utilization of simulation resources and hardware 29

30 Qualifying statement for nodes definition What are internal or external nodes? For JivaroGG there are 2 types of nodes: External nodes: Primary ports (* P in dspf) and Instance ports (* I) Internal nodes The external nodes cannot be reduced, only internal nodes can. VDD Parasitic devices VDD VDD Non parasitic devices IN OUT IN OUT IN OUT VSS VSS VSS Primary port Instance port Internal node Schematic Layout RC extracted netlist Page 30

31 Graphical Interface A graphical interface to select the database view to reduce and to set JivaroGG reduction options is available under Analog Design Environment (Tools->Jivaro Parasitic Reducer ) Page 31

32 Reduction test cases Oscillator Receiver extracted reduced ratio extracted reduced ratio res % cap % ind Internal nodes % CPU: CR 50m 28s 17m 06s memory 4089M 1479M res % cap % ind Internal nodes % CPU: DC 4h 11m 1h 6m memory 4652M 3093M Page 32

33 Reduction test cases, continued Transmitter VCO extracted reduced ratio extracted reduced ratio res % cap % ind Internal nodes CPU:CR % 11h 37m memory??? 65863M res % cap % ind Internal nodes % CPU:CR 52m 51s 10m 49s 80% memory 3269M 394M 88% Page 33

34 Power amplifier with WLAN signal (2) Virtual Test Bench replaces source. Results taken from output node This is same schematic as SP, gain comp., IP3 simulations 34

35 Specify Virtual Test Bench parameters From ADE window Specify frequency, power, source filtering, measurement types, etc. 35

36 Automatically-generated results Out of specification Simulation takes only about 20 seconds to measure 3 frames of data! 36

37 Sweep modulated source power Simulation takes only about 2 mins. 10 seconds! 37

38 Examples 38

39 LNA degradation due to noise, blocker (1) Simulation test bench LNA subcircuit Spirals modeled using Momentum 39

40 Reducing input power degrades constellation, spectrum, and EVM 40

41 With blocker tone at input Sinusoidal blocker power and offset frequency may be set arbitrarily. May have multiple blockers. All these simulations use the same test bench. 41

42 Examples 42

43 Power amplifier simulation with LTE signal LTE source and sink components exported from ADS Ptolemy. 43

44 LTE source and sink parameters Source Sink All parameters are from original Ptolemy schematic. Modify as needed or use defaults. 44 May 19, 2009

45 LTE simulation outputs (1) 45

46 LTE simulation outputs (2) 46

47 Examples 47

48 Raw EVM of baseband chains I-channel baseband chain Baseband I in (t) I and Q modulation source Q in (t) I 1 (t) Q-channel baseband chain Q 1 (t) I 2 (t) Q 2 (t) Relatively fast simulation. Shows where and how much degradation occurs. Q in (t) I in (t) Q 1 (t) I 1 (t) Q 2 (t) I 2 (t) 1) If needed, correct for average gain, phase shift, and delay. 2) How well do vectors match input vector, at each time point? 48

49 Simulation test bench Analog filter with tunable bandwidth Baseband source exported from Ptolemy Voltage-controlled voltage sources enable differential signal with DC bias at input 49

50 Simulation outputs Specify reference (input) and test (output) vectors. Prior to adjusting time delay After adjusting time delay 50

51 EVM improvement after increasing filter bandwidth Simulation takes about 9 minutes 51

52 Specification-compliant EVM requires sink from Ptolemy Sink parameters Baseband source exported from Ptolemy Baseband sink exported from Ptolemy 52

53 Specification-compliant simulation outputs With original, too-narrow filter bandwidth 53

54 Comparing raw and specification-compliant EVMs Filter bandwidth= 7.77 MHz Filter bandwidth= MHz Raw EVM 18.8% 9.1% 9 minutes Simulation time (for each filter bandwidth setting) Specificationcompliant EVM % % 2 hours, 1 min., for three frames 54

55 Examples 55

56 Receiver simulation test bench DC offset cancellation circuit Variable gain amplifiers WLAN RF source exported from Ptolemy LN A LO signals generated from Noisecor files Tunable, analog lowpass filter 56

57 Calculated raw EVMs Test points raw EVM LNA output 3.3% Mixer outputs 3.5% DC offset cancellation circuit outputs 2.3% 1 st variable gain amplifier outputs 2.2% Tunable filter outputs 12.8% 2 nd variable gain amplifier outputs 12.4% Most degradation occurs in baseband low-pass filters. 100 usec. simulation takes 50 minutes. A BER simulation would take days. 57

58 Examples 58

59 How does EVM change at various points as VGA gain is adjusted? VGA gain versus control voltage I-channel baseband chain I 1 (t) I 2 (t) I in (t) Baseband I and Q mod. source Q-channel baseband chain RF in (t) Power RF in Amp RF out (t) Q in (t) RF out (t) RF in (t) Q in (t) Q 1 (t) Q 2 (t) I in (t) I 1 (t) I 2 (t) 59

60 Raw EVM table VGA Control Voltage Simulation time: 3 hours 59 minutes. Shorten by reducing number of swept values. Filter Outputs VGA Outputs Mixer Outputs Power Amp. output % 13.1% 13.1% 12.9% % 18.0% 18.2% 17.5% % 20.6% 21.3% 19.3% % 18.1% 19.3% 18.2% % 13.5% 13.6% 11.8% % 10.7% 9.7% 16.2% Filter contribution to EVM is roughly constant VGA contribution to EVM varies a lot Power Amp only contributes to EVM when VGA gain is at its maximum 60

61 RF/Mixed-Signal Verification Transient / Verilog-AMS Co-sim Problem: RF and mixed-signal blocks are simulated separately today PA with digital control / linearization AGC, PLL DAC Digital Filtering Solution: Transient / Verilog-AMS Co-sim Simulate a combination of RF transistor level blocks and digital/mixed-signal blocks Full AMS support via co-simulation with a 3rd party digital simulator (ModelSim, NCsim) New GoldenGate Verilog-AMS Co-sim Module Future: Envelope / Verilog-AMS Co-sim (2009) Digital Simulator Page 61

62 RF/Mixed-Signal Verification Digital State Sweeps Digital Control Circuitry RF Circuitry Problem: increasing use of digital control circuits driving RF circuits Today, digital control circuits are replaced by idealized sources for RF simulation Simulations are manual, error-prone Solution: Digital State Sweeps Use VCD files from digital simulations to automatically drive RF simulations Quickly sweep through all control states Discover mixed-signal interface problems earlier in the development process Digital Simulation VCD File RF Simulation DSF File Page 62 Agilent Restricted

63 Digital State Sweep Example -- Variable Gain Amp Swept Gain at 16 digital control states Control voltage vs. control state Gain vs control voltage Page 63 Agilent Restricted

64 GoldenGate DFY Tools & Capabilities Fundamental DFY Capabilities Corners, Monte Carlo Correlation Analysis Yield Analysis Block Specific Statistical Variation Trial Rerun Advanced Sampling Algorithms Latin Hypercube Sampling Hammersly Sequence Sampling Boundary Mode Orthogonal Arrays Parallel Simulation Tools Job Manager Parallel Monte Carlo Controller Quad Pack Licensing Parallel MC/Corner Licensing Variable #2 x x x x x x x x x x x x x x x Variable #1 Page 64

65 GoldenGate Advanced Monte Carlo Modes Variable #2 Monte Carlo x x xx x x x x xxx xxxx x xx xxx xx xx x x x xxxx x x x xx xx x x Variable #2 Quasi Monte Carlo (LHS, HSS) x x x x x x x x x x x x x x x Variable #1 Variable #1 Corners Boundary Boundary Orthogonal Array Variable #2 x x x x Variable #2 x x x x x x x x x x x x x Variable #2 x x x x x x Variable #1 Variable #1 Variable #1 Page 65

66 Q Monte Carlo Controller (QMCC) Graphical cockpit to control parallel Monte Carlo and Corners More efficient dispatch based mechanism reduces idle time Supports LSF, Grid Engine, Local - ability to inspect and load balance Page 66

67 Summary GoldenGate enables you to: Use modulated signals for both design and verification Use raw EVM to quickly predict performance and find problem areas Run specification-compliant simulations for verification 67