Project Title: 60GHz CMOS Radio

Transcription

1 Project Title: 60GHz CMOS Radio Prepared By: Efstratios (Stan) Skafidas (Supervisor) and Ph.D. students :Jerry Liu, Chang (Aleck) Liu, Byron Wicks,Gordana Felic, Chien Ma Tien, Bo Yang, Yu Feng, Yuan Mo, Ke Wang, Frank Zhang Institution: Sensor Networks Program, Victorian Research Laboratory, National ICT Australia. Date of Submission: December 2006

2 60 GHz Radio Project Description The recent allocation of spectrum in the 57 to 64 GHz band has provided an opportunity to achieve wireless gigabit-per-second data-rate and transition from a centralized deployment to an ad-hoc wireless mesh deployment, facilitating self configuring, self organizing and self managing networks. The project will deliver an RF transceiver designed specifically for C. It will operate the 57-64GHz band and achieve gigabit speed operation. The IC will include all circuitry required to implement the RF transceiver function, providing a fully integrated receive path, transmit path, VCO, frequency synthesizer, and baseband / control interface, PA, RF bandpass filters (BPF), RF baluns, with minimal external passive components. Fabrication Process IBM 8RF-DM process Packaging Requirements Devices will be cut unpackaged-die. These will be mounted on an appropriate substrate to facilitate high frequency (60GHz) probing. Estimated Project Size Radio (5mm x 5mm) on IBM 8RF-DM process Simulation Plans Top Level Simulation Regression Suite 1. A top level behavioral system simulation model will be built in Synopsys Cocentric studio. The model will contain RF / mixed signal and digital baseband and medium access controller components. This system will form the basis of the regression suite. 2. A comprehensive set of test cases will be generated to ensure that every component of functionality specified in the architecture and specification document is tested. Each test case has a set of stimuli and expected outputs. 3. The top level simulation will include non-idealities such as thermal noise, PA non-idealities, LNA dynamic range limitations, DC Offset, I and Q imbalance and Phase and Flicker noise. The simulation test bench will have the capability to switch on and off these non-idealities to ensure that subtle mistakes are not masked by these non-idealities. RF Subsystem simulation suite 1. A RF system simulation suite will be created. The top level simulation suite will be created in Spectre RF. 2. Each cell will have a Schematic, Layout and Extracted Layout view.

3 3. For each cell/block a test bench will be created. The test bench will specify a set of bias and temperature conditions and will generate a set of inputs. 4. Each cell s schematic will be simulated Cadence Spectre simulator. Simulations will be performed on schematic and post layout RCLK extracted view. 5. The outputs of the analog/rf blocks will be included in the Top Level simulation and a top level simulation will be performed. This will ensure the analog components are adequate for satisfactory performance. 6. A Layout of each block will be completed. This will be followed by DRC and then each cell s schematic and layout will be compared using a LVS tool. 7. Parasitic Extraction will be performed for each cell/block 8. If possible a complete transistor level RF subsystem simulation will be performed. This may not be possible because of the large size of the design and the time that it would take to complete the design. Test and Characterization Plan Test for Design The specific tests for each component are described in the appropriate component section. Table of Characterization Tests that will be performed on the RF system Parameter LNA PA Mixer Switch Trans mitter Recei ver VSWR X X X X Return Loss X X X X X Insertion Loss X X Gain X X X Gain Flatness X X Isolation X X X Linearity X Noise Figure X X X X Dynamic range X X Power Compression X X X X X X IP3 X X X X X TOI X X Harmonic Distortion X X X Conversion Loss/Gain X Intermodulation Distortion X Switching Speed X Bandwidth X X X X X X Spurious Output X X X RF-LO Rejection X X ACPR-ACLR X X Phase Noise X X I/Q Offset X

4 I/Q amplitude mismatch X I/Q Phase Mismatch X Output Power X X EVM X X Table 1 RF Radio Transceiver Characterization Tests Power Amplifier Implementation of the first Doherty 60 GHz Power Amplifier on 130nm Technology. Fabrication process IBM CMRF8SF Packing Requirements None Estimated project size (length and width). 2,000 um * 2,000u Simulation plans Cadence ADE / Spectre RFDE / Momentum Test and Characterization Plans For this design the following tests will be performed 1. S-Parameters (S11, S12, S21, S22) 2. Noise Figure 3. IP3 4. P1-dB Compression Point 5. PSat 60 GHz PA 5 Cascode Stage

5 Layout Layout of Class A amplifier required to build a Doherty Amplifier Monte Carlo (3 27 degrees C

6 Noise Figure Transient Response Layout

7 S-Parameters Layout of Completed Doherty Amplifier to operate at 60GHz Marchand Balun Expected Performance (i) Measured Parameters: 3-port S-parameters S11, S12, S13, S21, S22, S23, S31, S32, S33, at frequencies 0-80GHz (ii) Evaluated Parameters from 50-70GHz Amplitude balance S AB = 20 log 10 S and Phase balance: S PB = ang S Layout 31 21

8 ( ) (db) Amplitude Balance Frequency (GHz) Simulated 3D EM (HFSS) simulation of expected amplitude balance Phase Balance d e g r e e s Frequency (GHz) Simulated 3D EM (HFSS) simulation of expected phase balance

9 (db) S11 Frequency (GHz) Simulated 3D EM (HFSS) simulation of expected insertion loss

10 Transmit/Receive Switch design project 1. Project description Design a Transmit/Receive Switch operating at 60 GHz band using CMOS technology. 2. Fabrication process IBM CMRF8SF 3. Packaging requirement: NONE 4. Estimate project size: 900um x 700um 5. Simulation plan S-parameter simulation within Monte-Carlo simulation S-parameter simulation within Corner simulation P1dB compression simulation with PSS IP3 simulation with PSS ESD protection simulation Post-layout simulation (S-parameter only) 6. Test and characterization plan Three-port S-parameter measurement Open-Short de-embedding for S-parameter measurement P1dB measurement IP3 measurement ESD protection measurement 1. Layout

11 Size: 700um x 530um 2. Expected performance Frequency range Insertion loss Isolation Input and output matching Input P1dB 57 GHz 66 GHz 5dB 33dB <14dB

12 Insertion loss Isolation Input and output matching

13 1-dB Compression point LNA Layout Picture and Post-layout Simulation Results Layout Picture: Description

14 The aim of this circuit is to develop a Low Noise Amplifier operating at 60GHz on 130nm bulk CMOS. The circuit is designed using classical techniques maximizing gain and minimizing noise figure. The post layout results of this circuit are illustrated in the graphs that follow Nominal Amplifier Gain Versus Frequency Noise Figure Versus Frequency

15 S22 S11

16 Project description: High speed 6-bit flash A/D Fabrication process: CMOS8RF MA Estimated project size (length and width): Length: 1000um Width:900um Simulation plans: 1. Design components of the A/D, e.g. digital logics, comparators, encoders, resistive ladders, using IBM PDK ver models in Cadence Schematic Editor. 2. Simulate performance of components in Cadence Analogue Design Environment, e.g. timing, glitches, power. Based on the simulation result, tone the circuit. 3. Combine all components to form the A/D 4. Simulate A/D performance, DC simulation (DNL, INL), dynamic testing (SFDR, SNR, SNDR, ENOB, power), Monte Carlo simulation (Process and mismatch at different temperature). 5. Simulate the design after post layout simulation (RCLK) Test and characterization plans: 1. Test Parameters: (i) Measured Parameters: DNL, INL, SFDR, SNDR, SNR, Power (ii) Calculated Parameters: ENOB, DNL, INL 2. Test Device: (i) DC/AC Signal Source (Programmable) (ii) The Suss-Microtech Probe Station with a couple of 8-10 tip probe. (iii) High accuracy high speed D/A (iv) Logic Analyzer (v) Personal Computer (vi) Low Pass Filter (vii) Spectrum Analyzer (optional) (viii) Analog Distortion Analyzer (optional) 3. Test Procedure: (i)dc test: DNL, INL, power, offset error, full-scale error Apply a slowly varying analog input signal across the full range to plot the error of each conversion step and calculate DNL/INL accordingly. (ii)dynamic test: SFDR, SNR, SNDR, power Apply high frequency sine wave signal to the A/D. Store the 6-bit digital output in a PC. Then use FFT to analyze data to get SFDR, SNR and SNDR. Calculate ENOB. (iii)temperature and Supply Voltage Variation Perform DC and AC test in room and high temperature environment. Vary the power supply and perform the DC/AC test. Performance 2GSPS, 6bit Analog-to-Digital Converter Power: 100mW average DNL: <1 LSB INL: <1 LSB

17 ENOB: 5.7bits SFDR: 36dB

18 On Chip Band Pass Filters built on CMOS Description: In this project 60GHz Band Pass Filters will be build on CMOS. One of the filters will tuneable Fabrication process: Utilizing IBM CMOS8RF process. Estimated project size (length and width). Without Pads and Pad edges/including Pads and Pad edges Design 1: 2-pole square BPF: 687.6um x 338.8um/900um x 600um Design 2: 2-pole rectangular BPF: 502.8um x 415.5um/750um x 700um Design 3: 4-pole square and meandering rectangular BPF: 689um x 570um /900um x 800um Design 4: TBD According to the space arranged, 1-2 open de-embedding structures and maybe 1 short de-embedding structure will be added. Open 1 - for design 3 and maybe 1 and 4/for all: 900um x 800um Maybe also including following structures: Open 2 - for design 2 and maybe 1: 750um x 700um and/or Short - for all: 490um x 290um Simulation plans. 1. Using Math tool to calculate theoretical parameters;

19 2. Using Math tool and 3-D EM (Electromagnetic) Full-Wave simulator - Ansoft HFSS (High Frequency Structure Simulator) to calculate and optimize the physical dimensions; 3. Using Ansoft HFSS to simulate the complete structure to get the S-parameter, and may make the sensitivity analysis; 4.Using Assura Layout tool to layout the final designs. (If active components included, the ADS (Angilent Design Software) may be used to carry out the final simulations.) Test and characterization plans. 1. Test Parameters: (i) Measured Parameters: 2-port S-parameter S11, S21@0-80GHz, especially 49-74GHz (pass band bandwidth: 57-66GHz); (ii) Calculated Parameters: Pass band bandwidth; VSWR (Voltage Standing Wave Ratio): 1+ S11 VSWR = 1 S11 IL (Insertion Loss): IL = 20log S21 2. Test Device: (i) One 110GHz VNA (Vector Network Analyzer); (ii) The Suss-Microtech Probe Station with a pair of RF Probe Tips. The Probe Tips have G-S-G (Ground-Signal-Ground) structure and are able to make measurements up to 110GHz; (iii) Mathematic tool Matlab; 3. Test Structures including four kinds of structures: (i) DUT (Device Under Test):

20 Guard Ring Pads DUT DUT (ii) Open structure:

21 Guard Ring Pads Open Structure (iii) Short structure: Short Structure 4. Test Procedure: (i) VNA s Calibration: skipped for most cases; (ii) Probe Station s Calibration: utilizing LRM+ (Line-Reflect-Match+) method;

22 (iii) Making measurements of S-parameter: DUT measurement, Open structure measurement, Short structure measurement; (iv) Making De-embedding: utilizing the mathematic tool (here Matlab will be used) with OD (Open De-embedding), or OSD (Open-Short De-embedding) methods; (v) Display the final two-port S-parameter and calculate parameters shown in above 1-(ii); (vi) Making measurements of structures on different dies, so as to indicate the effect of fabrication variations. Post Layout Bandpass filter Structure

23 3D EM Simulation (HFSS) of layout

24 Tuneable Bandpass filter (2GHz Bandwidth Tuneable from 57-66GHz)

25 Proposal of frequency dividers fabrication submission 1. Estimated Size of frequency divider (1). 60 GHz frequency divider, division ration is 2, size of 1.15mm 0.85mm; (2). 30 GHz frequency divider division ration is 2, size of 1.175mm 0.95mm; (3). Combining 60 GHz divider + 30 GHz frequency divider, size of 1.175mm 2.102mm 2. Measurement Aims: To measure Free-running Frequency Tuning Range [GHz] Division Range [GHz] Phase Noise [dbc / Hz] Power Dissipation [mw] Frequency Stability of Temperature [%] Frequency Stability of Voltage supply [%] 3. Test Methods 3.1 Free-running Frequency Without any input signal, just switch on the Vdd and change the value of the control voltage to test the divider s free running frequency. This measurement could be realized from the spectrum analyzer using peak search function. The final result will be plotted in a grid graph with frequency measurements versus control voltage. 3.2 Division Range Firstly turn on the divider until its free-running state is stable, and then inject the signal from 57 GHZ to 66 GHz for (1) and (3), and 28.5 GHz to 33 GHz for (2). The final result will be plotted in a grid graph with frequency of input and output measurements together versus control voltage. 3.3 Phase Noise Free-running Frequency Phase Noise

26 Under this status, the divider acts as a VCO, so that the phase noise (which is SSB) is directly tested by drift frequency spectrum analyzer and the result will be plotted with noise power blow carrier (dbc / Hz) versus offset frequency. Injection Phase Noise In this state, noise is injected from noise source to divider; it is measured by frequency spectrum analyzer. We can change the power of injected signal to observe the different results. And then the results are to be plotted in the same figure of free-running phase noise to compare the results. 3.4 Power Dissipation This could be measured of high frequency power meter both at free-running and injection status. 3.5 Temperature Variation Measure the frequency drift under different temperature from 25 0 C to 75 0 C, and then give the drift percentage of frequency of free-running and injection status. 3.6 Variation of Vdd Under different Vdd variation of ± 20%, test the offset percentage of free-running frequency. Estimated size: u X 600u u X 500u u X 1000u u X 1000u Simulation Plans: 1. Transient simulation 2. PSS PNOISE simulation 3. Monte Carlo simulation for process and temperature variation Test Plan for RF front-end Voltage Controlled Oscillator (VCO) 4. Measurement Aims: To measure Frequency and Tuning Range

27 Phase Noise Power Output 5. Apparatus: DC supply (need 5 inputs) Spectrum Analyzer Power Meter 6. Test Structures: 7. Test Methods: 1. The VCO frequency is changed by changing the tuning voltage. Different frequency is read from the spectrum analyzer using peak search function. 2. The frequency measurements are plotted against the tune voltage. The slope of this characteristic is the tune voltage sensitivity and can be calculated at different tune voltages. 3. In addition to frequency, power and long-term stability, short-term stability or its equivalent, phase noise, is an important characteristic. The simplest and fastest method of determining phase noise is the direct measurement by means of a spectrum analyzer. The oscillator drift must be small relative to the spectrum-analyzer sweep time since otherwise the oscillator frequency varies during the sweep, leading to distorted results. The phase noise of the local oscillators of the spectrum analyzer must be low enough to ensure that the characteristics of the DUT rather than those of the spectrum analyzer are determined. 4. Power output is measured by means of high frequency power meter.