Direct-Conversion I-Q Modulator Simulation by Andy Howard, Applications Engineer Agilent EEsof EDA
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1 Direct-Conversion I-Q Modulator Simulation by Andy Howard, Applications Engineer Agilent EEsof EDA Introduction This article covers an Agilent EEsof ADS example that shows the simulation of a directconversion, transistor-level I-Q modulator. Included are differential-mode mixers, a combiner, a buffer, and a power amplifier. Many simulations of the sub-circuits as well as the modulator are included: Amplifier gain compression, load pull, ac frequency responses, mixer intermodulation distortion as a function of various swept parameters, modulator amplitude and phase accuracy, simulations with CDMA baseband data sources, and others. Many of the simulations would be almost impossible to complete with a purely time-domain simulator such as SPICE. The design has not been fabricated, and is instead used as an example to show simulation capabilities. The time has not been taken to extensively optimize this design by reducing power consumption, minimizing bias voltages, etc., although the various simulation set-ups could be used to improve the design. Also, bias circuitry has not been included. A number of different simulations have been run on each of the different parts of the modulator, as well as simulations on the parts combined together. Our assumption was that a designer would not just throw the entire modulator together at once, and that there would be shortcomings that would be improved more easily by simulating one part of the modulator at a time. The I-Q modulator design I-Q (In Phase-Quadrature), or vector, modulators are commonly-used integrated circuits in modern communications equipment. These modulators operate by taking two baseband data sequences (I and Q channels) and varying the amplitude and phase of a sinusoidal carrier signal in response to the instantaneous I and Q channel voltages (Refs. 1 and 2.) Designers of these ICs must be concerned with the specific performance characteristics of modulation accuracy, dynamic range, frequency response, undesired leakage and intermodulation distortion, as well as more general characteristics like power consumption, efficiency, and output power. In the example direct-conversion I-Q modulator, a 960-MHz LO signal is directly modulated by baseband I and Q data signals. The modulator consists of a mixer, a combiner, a buffer, which also converts a differential-mode signal into a single-ended signal, and a power amplifier. A 960- MHz 90-degree phase shifter has not been included. Instead, ideal LO signals are generated by the simulator. Simulations are also run with amplitude and phase imbalances to see their effects. The specific design for this modulator is shown in Fig. 1.
2 Fig. 1: I-Q Modulator: Mixer, Combiner, Differential-Input Buffer & Power Amplifier A number of different simulations have been run on each of the different parts of the modulator, and on the combined parts. Simulations of each part of the modulator are described below, starting with the power amplifier output stage and progressing backward through the circuit. Power amplifier The power amplifier (low power output buffer) takes a voltage input and converts it to a current, required to drive an off-chip large-signal amplifier for higher output powers. The topology consists of an emitter-follower stage driving three emitter-followers in parallel (Fig. 2.) Fig. 2: Schematic Of The Power Amplifier
3 To begin, an S-parameter simulation of the devices used in the amplifier verifies that they will provide gain at the desired operating frequency. However, S-parameter analysis is linear only and does not provide distortion or output power information. A simulation of the dc input-output transfer curve of the amplifier (Fig. 3) helps select the best bias voltage for the input signal, to get the maximum dynamic range without clipping. This will not provide the maximum efficiency, but for modulation formats that include both amplitude and phase minimizing distortion is more important than dc power consumption (at this low power.) The markers (Fig. 3, again) are used to calculate the optimal input bias point, although this might require modification if the previous stage is unable to output the 5-V rail voltage. Fig. 3: The Amplifier s Dc Transfer Curve, With Open-Circuit Output To evaluate the output power, dc-to-rf efficiency, and 3rd- and 5th-order intermodulation distortion versus load impedance, a load-pull simulation was run at one bias point. In this simulation, a circular region of the Smith chart is specified, with load impedances within this region presented to the output of the amplifier (Fig. 4.) The dc-to-rf efficiency can be increased somewhat by driving the amplifier with a larger input signal, but at the expense of increased distortion.
4 Fig. 4: Simulation Results For Dc-To-RF Efficiency/Delivered Power Contours Fig. 5 shows the simulated load impedances, output spectrum, intermodulation distortion and output waveform for two-tone load-pull simulation. Using this data with the contours of Fig. 4, you can quickly determine how changes in the load impedance affect the output power, efficiency, and level of intermodulation distortion products, as well as the shape of the output waveform.
5 Fig. 5: Outputs From The Two-Tone Load-Pull Simulation The Power Amplifier DesignGuide in ADS was then used to determine component values for a simple series-l, shunt-c, series-c matching network that presents the desired load impedance to the amplifier at 960 MHz. A swept amplitude simulation was run to evaluate output power compression, intermodulation distortion and output waveforms vs. the amplitude of the input signal. Fig. 6 shows the simulation setup.
6 Fig. 6: Simulation Setup For Amplifier Output Power Compression And Intermodulation Distortion The results of the simulation are shown in Fig. 7 with the output power, efficiency, and intermodulation distortion characteristics, all as a function of input signal amplitude. From these plots and the columns of listed data, you can quickly determine the level of distortion produced by the circuit for a given input signal level.
7 Fig. 7: Output Power Compression And Intermodulation Distortion Simulation Results One additional characterization test, a one-tone simulation, was run with a sweep of two parameters: The emitter resistor in each of the three parallel output stages (which sets the bias current); and the input bias voltage. Of course, other parameters could be swept to determine performance improvements or identify sensitivities. The results of this simulation are shown in Fig. 8, which shows the trade-offs that can be made between output power, dc-to-rf power efficiency and dc bias current consumption. These plots also show the flexibility in ADS for presenting data, making it easier for designers to evaluate trade-offs and optimize designs.
8 Fig. 8: Amplifier Output Power And Dc-To-RF Efficiency Vs. Input Bias Voltage And Output Stage Emitter Bias Resistor Value Differential Input To Single-Ended Output Buffer Fig. 9: Differential- And Common-Mode Gain Simulation The differential input to single-ended output buffer is required because the baseband circuits operate in the differential-mode, while the output amplifier is single-ended. The simulations of this circuit include the dc transfer characteristic, along with differential- and common-mode small-signal gains and common-mode rejection ratio versus frequency. The setup for simulating both the common- and differential-mode gains is shown in Fig. 9. The variable ph is set to two values, 0 and 180, which changes the polarity of one of the input
9 signals and allows both common- and differential-mode gains to be simulated from one set-up. Fig. 10 shows the simulation results. Fig. 10: Differential Input To Single-Ended Output Simulation Results Combiner This circuit combines the two differential-mode input signals from the mixers into a differentialmode output signal. Like the differential-to-single ended converter, the simulations of this circuit include the dc transfer characteristics, as well as the differential- and common-mode small-signal gains and the common-mode rejection ratio, vs. frequency. Mixers Two differential-mode mixers, similar to Gilbert cells, are used to directly modulate the two quadrature LO signals with the baseband I- and Q-modulation waveforms. The diagram of the two mixers is shown in Fig. 11. Although the schematic is too small to see the details, it shows the topology that was used.
10 Fig. 11: ADS Schematic Of The Two Identical Mixers, Which Include A Total Of 48 BJTs Because they perform frequency conversion, characterizing mixer performance is more complex than it is for circuits like amplifiers. Our first characterization is of the conversion gain, plus second- and third-order intermodulation distortion vs. baseband signal amplitude. The simulation setup is shown in Fig. 12.
11 Fig. 12: Simulation Setup For Mixer Conversion Gain And Intermodulation Distortion In the mixer simulation, the 960-MHz LO signal is modeled as a pulse waveform. Two baseband signals are defined, spaced 20 khz apart and centered at 1 MHz, although these frequencies may be set arbitrarily without affecting simulation performance, a flexibility that is not possible with some time-domain based simulators. The amplitudes of the two baseband signals are swept from 5 mv to 35 mv. Fig. 13 shows the simulated output spectrum over narrow and wider frequency ranges.
12 Fig. 13: The Simulated Mixer Output Spectrum For One Input Signal Amplitude, Shown In Two Frequency Ranges. These Spectra Are Updated When The Marker Is Moved Fig. 14: Simulation Results For Mixer Conversion Gain And Intermodulation Distortion Vs. Baseband Signal Amplitude
13 Additional simulation results (Fig. 14) indicate that the conversion gain starts to decrease as the input signal amplitude is increased towards 35 mv, and that the intermodulation distortion level rises, both as expected. Although not included here second-order intermodulation distortion calculations are provided in the example file. Simulations were also run to characterize the mixer s performance vs. LO signal amplitude and baseband signal frequency, with some of the results shown in Fig. 15. These simulations help to determine the optimal baseband and LO signal amplitudes, as well as ensure that the frequency response of the mixer will not distort the modulation signal. Fig. 15: Mixer Conversion Gain/Intermodulation Distortion Vs. LO Signal Amplitude Simulating The Entire Modulator After simulating each element individually, the next step is to simulate the performance of the entire modulator. Ideally, the output signal should be proportional to, I ( t) *sin( ω ct) + Q( t) *cos( ω ct), where I(t) and Q(t) are the baseband modulation signals and ω c is the carrier, which is also the LO frequency in a direct-conversion modulator. By applying different I and Q baseband signals, you can characterize the modulator s accuracy, intermodulation distortion, error-vector magnitude, output power compression, LO leakage and other performance factors. If the baseband modulation signals are sinusoids with a phase difference of 90 degrees, I ( t) = Vbb *sin( ω mt) and Q( t) = Vbb *cos( ω mt), then an x-y plot of the Q signal on the y-axis versus the I signal on the x-axis creates a circle. When these signals are applied to the I-Q modulator, the trajectory diagram (envelope of the modulated carrier) should also trace a circle of constant amplitude and constant rate of phase change. Any deviation from this ideal response is due to distortion or mismatches in the
14 modulator, or amplitude and phase imbalances in the LO. The simulation can use ideal LO signals, or include LO amplitude and phase imbalances and see their effects on the modulator s performance. The ADS Circuit Envelope simulator is particularly well suited for this type of simulation. Fig. 16 shows a setup for simulating the single-sideband modulator output versus baseband signal amplitude. In this example, a 3-degree phase error and 5 percent magnitude error have been introduced, creating non-ideal LO signals. The baseband signal amplitude has been swept from 1 mv to 30 mv. Fig. 16: Simulation Setup: Modulator Output (SSB Case) Vs. Baseband Signal Amplitude Some of the simulation results are shown in Fig. 17. The output spectrum with baseband signal amplitudes of 30 mv is shown, which may be updated for different input signal levels by moving a marker. The upper sideband signal level and the highest intermodulation distortion term versus input signal amplitude are also shown.
15 Fig. 17: A Portion Of The SSB Simulation Results Fig. 18 shows the variation in signal amplitude and phase error at the output and two other points within the modulator. These errors will vary somewhat with baseband signal magnitude. Fig. 18: I-Q Modulator Magnitude And Phase Error Simulation Results If the baseband modulation signals are in-phase sinusoids, I ( t) = Vbb *cos( ω mt) and Q( t) = Vbb *cos( ω mt), then the resulting output spectrum will be double sideband, centered on the LO frequency. Fig. 19 shows some of the simulation results, including the output spectrum when the baseband signal amplitudes are 10 mv, the upper sideband signal level and the highest intermodulation distortion term vs. input signal amplitude.
16 Fig. 19: Double-Sideband Output Spectrum, Plus The Output Power Of One Of The Fundamental Tones And One Of The Intermodulation Distortion Terms Vs. Input Signal Amplitude Finally, the modulator was simulated with baseband signals corresponding to various modulation formats, such as π/4 DQPSK and CDMA. Fig. 20 shows the modulator s output spectrum, output power, and adjacent-channel power levels, with baseband I and Q signals corresponding to the NADC π /4 DQPSK modulation format.
17 Fig. 20: Modulator Output Spectrum, Output Power, And Adjacent-Channel Power Levels, With NADC π/4 DQPSK Modulation Baseband I And Q Signals Fig. 21 shows the output trajectory and constellation diagrams, the error vector magnitude (EVM) in volts versus time, plus a readout of the percent EVM. This simulation was with no LO amplitude or phase imbalance. Arbitrary values of these imbalances can be introduced to evaluate the EVM degradation.
18 Fig. 21: Output Trajectory, Constellation Diagrams, And Error Vector Magnitude Data Fig. 22 shows the same simulation results as Fig. 21, but with a 3 percent LO phase imbalance and a 5 percent LO amplitude imbalance. The trajectory diagram shows increased distortion and the error vector magnitude is higher, as expected. Fig. 22: Output Trajectory, Constellation Diagrams And Error Vector Magnitude Data, With LO Phase And Amplitude Imbalance Effects Included I and Q modulation signals may use any baseband time-domain data. A simulation was run with baseband signals corresponding to the IS-95 CDMA specification. The resulting spectrum, output power, and ACPR for one baseband signal amplitude scaling factor are shown in Fig. 23, with results for a scaling factor five times as high shown in Fig. 24. There is a noticeable tradeoff between output signal power and ACPR.
19 Fig. 23: Output Spectrum, Main Channel Power, And ACPRs With A Baseband CDMA Signal
20 Fig. 24: Output Spectrum, Main Channel Power, And ACPRs With A Baseband CDMA Signal At Five Times The Amplitude Of The Signal Used In Fig. 23 Summary The design process for I-Q modulators requires many advanced simulation tools, as well as highly flexible methods of displaying the results. This paper has shown the wide range, and often unique, simulation and data display capabilities in the Advanced Design System that allow efficient, accurate simulation and characterization of I-Q modulators and their sub-circuits. For more information on ADS, or this application, visit References 1. Jim Wholey Vector Modulator ICs for Use in Wireless Communications, Proceedings of RF Expo West, 1993, pp
21 2. Digital Modulation in Communication Systems An Introduction, Hewlett-Packard Application Note 1298, The ADS IQ modulator example discussed in this article may downloaded from the Agilent Web site: The file name is IQ_Mod_from_MDS_prj.zap. Author s Bio Andy Howard joined HP in 1985, as a development engineer designing microwave circuits. He spent a year in Japan as a systems engineer before becoming an HP EEsof applications engineer in His applications work has included simulating noise in nonlinear circuits, high-yield design techniques (design of experiments), circuit envelope applications and, for the past four years, Agilent ADS examples. He developed the ADS Power Amplifier DesignGuide, and also worked on the Mixer DesignGuide. Earlier this year he designed a high-speed prescaler IC using Agilent s RFIC Dynamic Link. He earned a BSEE and MSEE from U.C. Berkeley and was a visiting researcher at NEC's Central Research Labs in Japan while a graduate student. He is fluent in Japanese.
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