Application Note 1330

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Andrea Boyd
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1 HMPP-3865 MiniPAK PIN Diode High Isolation SPDT Switch Design for 1.9 GHz and 2.45 GHz Applications Application Note 133 Introduction The Avago Technologies HMPP-3865 parallel diode pair combines low inductance, low capacitance and low package parasitics, increasing the maximum frequency at which silicon PIN diode switches may be used. The HMPP-3865 offers industry leading performance in terms of the critical parameters of insertion loss, return loss and isolation high isolation and low resistance increases the efficiency of the switching circuit, resulting in longer battery life in portable equipment. This application note will look at techniques used to minimize the effects of the package parasitics even further by resonating out the diode capacitance to produce a switch design with typically greater than 35 db of isolation and an insertion loss of.5 db. The design technique is then used to illustrate two High Isolation, SPDT switches at 1.9 GHz and 2.45 GHz. PORT 1 C3 C2 L1 PORT 3 C1 C2 C3 PORT 2 The Avago Technologies MiniPak package is only 1.4 mm x 1.2 mm, permitting smaller circuit boards. It is only.7 mm high, allowing closer board spacing, and offers improved thermal conductivity for higher power dissipation than other surface-mount packages. It is lead-free for compliance with emerging environmental requirements. Figure 1. Single Pole Double Throw (SPDT) Switch using HMPP-3865 PIN Diode In addition to the HMPP-3865 parallel diode pair, Avago Technologies also offers the HMPP-386 single PIN diode and HMPP-3862 anti-parallel diode pair in the MiniPak package.

2 Description The switch is operated by applying bias current to the diode in series with port 1 and the antenna, bringing it to a low resistance state. This connects port 1 to the antenna port. The bias current to the second diode is held off, making the diode high resistance. The use of a low series resistance and low series inductance PIN diode ensures low loss in the through path and is also good for high isolation. The equivalent circuit model for the HMPP-3865 is shown in Figure 2. This can be used in linear simulations by adjusting the two resistor values between 5 kω, the unbiased value, and 2.5 Ω the biased value with 5 1 ma applied. Refer to the RF Resistance vs. Forward Bias Current graph in the data sheet for other bias conditions. Alternatively, the PIN diode APLAC model can be used to replace the parallel capacitor and resistor in the model, as shown in Figure 3. The APLAC model is used to model the PIN diode die. More on this in the next section..5 nh.5 nh.5 nh nh 3 ff 2 ff 12 ff 2 ff.2 pf.5 nh.5 nh.5 nh 5.5 nh.2 pf 3 ff Figure 2. Equivalent circuit of HMPP-3865 using resistor/capacitor model 2 ff.2 pf.5 nh.5 nh.5 nh nh 3 ff 12 ff 3 ff.5 nh.5 nh.5 nh 5.5 nh.2 pf 2 ff Figure 3. Equivalent circuit of HMPP-3865 using APLAC die model 2

3 Table 1. APLAC PIN Diode Parameters for HMPP-386x Die Parameter, Units Unit Description Value R max, Ω Maximum r.f. resistance 5 R min, Ω Minimum r.f. resistance 1.5 K Resistance curve fitting exponent.9327 A Resistance curve fitting exponent.183 L, nh Connection inductance 2 C, pf Diode capacitance at r.f. frequency.2 Is A Diode saturation current 1.49E-9 N Diode ideality factor 2.22 TT nsec =Transit Time (carrier lifetime) 5 HMPP-386x Limited APLAC Model The APLAC PIN model consists of a current controlled resistor and a SPICE model for a diode. The APLAC PIN diode model is shown in Figure 5. D1 uses the standard SPICE diode model, and is described by I S, N, and TT. R S, in the standard model, is replaced by the external network of R min, R max, and R var. The parameters shown in Table 1 are for a single diode. Care should be taken not to include L, connection inductance, when used in conjunction with the package model. Parameters apply to the individual diodes within multiple diode configurations. The APLAC model is able to predict the RF resistance verses forward bias current. Figure 4 shows the RF resistance over a 1 µa to 1 ma range. At 1 MHz the RF resistance is approximately 7 Ω at.1 ma and 1.5 Ω at 1 ma. The results of the simulation can be checked against the characterization data shown in the HMPP-386x data sheet. The APLAC model assumes the R vs. I curve can be approximated using three resistors: RESISTANCE (OHMS) 1, 1, BIAS CURRENT (ma) Figure 4. RF Resistance vs. forward bias 1 MHz using APLAC model R max, R min, and R var. Where R var = A / I d K In this case the parameters A and K are shown in Table 1. In Avago Technologies' Advanced Design System (ADS), the current controlled resistor is implemented with a symbolically defined device (SDD). For more information on how to use these devices, refer to the Circuit Simulation manuals in ADS. C L R MIN R VAR D1 n1 R VAR = A/Id K n2 R MAX Figure 5. APLAC die model 3

4 L L L = L DIODE_MODEL DIODEM1 Is = 1.49nA N = 2.22 Tt= 5 nsec Cjo=.36 pf R R MIN R = R MIN VAR EQU SDD1P DIODE SDDNP1 DIODE1 I[ 1, ] = (_v1)/(a/((1e-26)+_c1)**k) C[1] = Id R R MAX R = R MAX VAR VA RMIN = 1.5 RMAX = 5 A =.183 K =.9327 L = nh C =.2 pf + C C C = C MODEL = DIODEM1 PERIPH = TEMP = MY TEMP DC_BLOCK DC_BLOCK1 DC_FEED DC_FEED1 I_PROBE Id Figure 6. PIN diode model implementation in Avago ADS using the published APLAC parameters Figure 6 shows the full implementation of the PIN diode model in ADS. The parameters for the SPICE diode model can be extracted from the measured DC IV curve and are also shown in Table 1. The final model includes the diode capacitance and connection inductance as shown in Figure 5. This model is valid for forward bias only when operated at frequencies above 1 Fc. Where, Fc = 1 / 2 Π τ τ is the minority carrier lifetime. The figure for carrier lifetime (τ) is an approximation for transit time (Tt). At 1 Fc and above the PIN diode behaves reliably as a variable resistor. The model will not correctly predict harmonics, however, it is useful in predicting RF resistance and the DC IV curves. This makes the APLAC model ideal for simulating PIN Diode switch and attenuator designs, where the RF resistance is varying with bias current. The APLAC model equation requires a small value of bias current in order to work. This is provided by the 1e-26 term in the symbolically defined device (SDD). If the term is omitted from the equation, the simulator will try to divide by zero and the equation will not be solved or will give an invalid result. 4

5 Demonstration Board Design Figure 7 shows the RF Layout of a demonstration board designed to allow SPDT switches to be built over a wide frequency range. Component values and results for two examples are given in this application note, at 19 MHz and 2.45 GHz. The assembly drawing for the board is shown in Figure 8. The switch design requires a high degree of isolation between one diode and the other. To facilitate this, the high isolation, PCB pad layout for the MiniPAK has been used. The pattern uses three via holes connecting the tee-shape ground pattern to the ground plane of the board. The pattern also has the desired effect of reducing the package capacitance. A dimensioned drawing for the ground pattern may be found in the assembly information section of the HMPP- 386x data sheet. IP 2-1 SPDT 1 MIL (25.4 mm) 78 MI (19.8 m The initial component values for these designs were determined from the linear simulation. Avago Technologies ADS EDA was chosen as the simulator. The circuit components can then be added to the simulation circuit. The more detailed the simulation the more accurate the results will be. An accurate circuit simulation can provide the appropriate first step to a successful switch design. The transmission line section can be modeled with various micro-strip and strip-line elements available in the component library. In this case, all micro-strip sections assumed a.8 mm (.31-inch) thick board and GETEC RG2D material. The inductance associated with the chip capacitors and resistors was also included in the simulation. Where possible, models were chosen from the ADS SMT component library. Models of SMT components can also be obtained from the manufacturers web sites. Manufacturing tolerances in both the active and passive components often prohibit perfect correlation. Figure 7. RF Layout for demonstration board The model for the HMPP-3865 was created and the create/edit schematic symbol function was used from the view menu in ADS. was chosen to be 39 Ω. From a 3 V supply, sets the diode bias current to approximately 5 ma. When using the APLAC die model, in the simulation, the effect of increasing or decreasing the bias current can easily be observed. The capacitors used were from ROHM MCH18 range and the inductors were TOKO types LL115. The TOKO inductors offer high Q, with typical values of 3 at 8 MHz. The printed board is designed to accept edge-mounting SMA connectors such as Johnson Components, Inc., Model These connectors are designed to slip over the edge of.8 mm (.31-inch) thick circuit boards and obviate the need to mount PCBs on a metal base plate for testing. IP 2-1 SPDT L1 C1 C3 C2 C2 C3 Figure 8. Assembly drawing for SPDT switch 5

6 Table 2. Component Parts List for the two frequencies. Frequency 1.9 GHz 2.45 GHz C1 5.6 pf 42 Chip Capacitor 5.6 pf 42 Chip Capacitor C2 1. pf 42 Chip Capacitor 1. pf 42 Chip Capacitor C3, 6.8 pf 42 Chip Capacitor 6.8 pf 42 Chip Capacitor 1 nf 42 Chip Capacitor 1 nf 42 Chip Capacitor L1 33 nh LL15-FH33N 22 nh LL15-FH22N 18 nh LL15-FH18N 12 nh LL15-FH12N 27 nh LL15-FH27N 33 nh LL15-FH33N 39 Ω 39 Ω Diode HMPP-3865 HMPP-3865 The switch design uses to resonate out the diode capacitance. By adjusting the value of the circuit can be tuned for high isolation over a range of 1 MHz typically. Higher values of can be used to move the switch maximum isolation to lower frequencies and lower values can be used to move the maximum isolation to higher frequencies. Typical values for the 1.9 GHz and 2.45 GHz design are shown in Table 2. For 1.8 GHz applications would be 22 nh and for 2.3 GHz applications would be 15 nh. Results Results from the simulation of the 1.9 GHz and 2.45 GHz example are shown in Figures 9 and 1 respectively. Measured results are shown in Table 3. INSERTION LOSS AND ISOLATION Figure 9. Simulation results for a 1.9 GHz high isolation switch INSERTION LOSS AND ISOLATION Figure 1. Simulation results for a 2.45 GHz high isolation switch 6

7 Table 3. Measured Insertion Loss, Isolation and Switching Speed Results. Frequency 1.9 GHz 2.45 GHz Port1 - Port3 Insertion Loss, db.5.6 Port1 - Port2 Isolation, db Port1 and Port3 Return Loss, db 17, 18 17, 19 Switching speed, On/Off, ns 18/36 18/36 Output 3rd Order Intercept Point, dbm Port 2 Return Loss, db.3.5 Summary The results obtained from the demo board described in the note show the potential use of the MiniPAK HMPP-3865 in a high Isolation SPDT switch design. Low insertion loss and high isolation compare with more costly RFIC GaAs switch solutions. Example applications are GSM18, PCS, DECT cordless phones, SDARS and 82.11b WLAN applications. Table 3 shows the typical measured results for the switch, with port 1 connected to port 3. Measured circuit results for the switch using the evaluation board for the 1.9 GHz and 2.45 GHz examples are shown in Figures 11 and 12 respectively. References Compact HSMP-389V Transmit/Receive Switch Design, Application Note A.R. Rixon Applications for the HSMP-389 Surface Mount Switching PIN Diode, Application Note 172 APLAC (Analysis Program for Linear Active Circuits) - Department of Electrical and Communications Engineering of the Helsinki University of Technology. Avago Technologies' Eesof Advanced Design System (ADS) electronic design automation (EDA) software for system, RF, and DSP designers who develop communications products. More information about Avago Technologies' EDA software may be found on - INSERTION LOSS AND ISOLATION Figure 11. Measured results for a 1.9 GHz high isolation switch INSERTION LOSS AND ISOLATION ( -1-2 S11, db S33, db -3-4 S11, db S33, db Figure 12. Measured results for a 2.45 GHz high isolation switch Performance data for Avago Technologies' HMPP-386x Series MiniPak Surface Mount RF PIN Diodes may be found on For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved EN - July 13, 21

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