MGA High Gain, High Linearity, Very Low Noise Amplifier. Features. Specifications

Transcription

1 MGA- High Gain, High Linearity, Very Low Noise Amplifier Data Sheet Description Avago Technologies MGA- is a two stage, easy-touse GaAs MMIC Low Noise Amplifier (LNA). The LNA has low noise with good input return loss and high linearity achieved through the use of Avago Technologies proprietary. m GaAs Enhancement-mode phemt process. Minimum matching needed for input, output and the inter-stage between the two LNA. It is designed for optimum use between MHz to. GHz. For optimum performance at higher frequency from. GHz to. GHz, the MGA- is recommended. Both MGA- & MGA- share the same package and pinout configuration. Pin Configuration and Package Marking. x. x. mm -lead QFN AVAGO YYWW XXXX TOP VIEW GND BOTTOM VIEW Note: Package marking provides orientation and identification = Device Part Number YYWW = Work Week and Year of Manufacture XXXX = Lot Number Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = V ESD Human Body Model = V Refer to Avago Application Note AR: Electrostatic Discharge, Damage and Control. Pin Pin Pin Pin Pin Pin Vbias RFinQ RFoutQ RFoutQ RFinQ RFoutQ All other pics NC Not Connected Features Optimum frequency of operation MHz. GHz Very low noise figure High gain High linearity performance Excellent isolation GaAs E-pHEMT Technology [] Low cost small package size:. x. x. mm Specifications MHz; Q: V, ma (typ) Q: V, ma (typ). db Noise Figure db Gain db RFoutQ to RFinQ Isolation. dbm Output IP. dbm Output Power at db gain compression Applications Low noise amplifier for cellular infrastructure including GSM, CDMA, and W-CDMA. Other very low noise applications. Simplified Schematic RFIN C C C R L R R Vdd C C L C Qbias Q R Q Vdd C C C L C RFOUT Notes: Enhancement mode technology employs positive gate bias, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices.

2 MGA- Absolute Maximum Rating [] TA = Symbol Parameter Units Absolute Maximum Vdd Device Voltage V. Vdd Device Voltage V. Idd Q Drain Current ma P d Power Dissipation () W. P in,max CW RF Input Power dbm T j,max Junction Temperature C T stg Storage Temperature C - to Thermal Resistance [] (V dd =.V, I dd =ma, V dd =.V, I dd =ma) jc =. C/W Notes:. Operation of this device in excess of any of these limits may cause permanent damage.. Board temperature (T c ) is. For T c > C, derate the device power at. mw per C rise in board temperature adjacent to package bottom.. Thermal resistance measured using Infrared Measurement Technique. Electrical Specifications [] RF performance at Vdd = V, V dd = V, MHz, T A =, measured on the demo board. Symbol Parameter and Test Condition Units Min. Typ. Max. Idd Current at Q ma Idd Current at Q ma NF Noise Figure db.. Gain Gain db.. OIP [] Output Third Order Intercept Point dbm.. OPdB Output Power at db Gain Compression dbm. IRL Input Return Loss, source db - ORL Output Return Loss, load db - S Reverse Isolation db ISOL - Isolation between Q s Output pin & Q s Input pin db Notes:. Measurements obtained using demo board described in Figure with component list in Table. Input and Output trace loss is not de-embedded from the measurement.. OIP test condition: f tone = MHz, f tone = MHz with input power of - dbm per tone.. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application note for more details.

3 Product consistency Distribution Charts [,] LSL USL LSL USL Figure. MHz, Vdd = V, LSL = ma, Nominal = ma, USL = ma Figure. MHz, Vdd = V, LSL = ma, Nominal = ma, USL = ma USL LSL USL Figure. Noise MHz, Vdd = V, Vdd = V, Nominal =. db, USL =. db Figure. MHz, Vdd = V, Vdd = V, LSL =. db, Nominal = db, USL =. db LSL LSL Figure. MHz, Vdd = V, Vdd = V, LSL =. dbm, Nominal =. dbm.. Figure. MHz, Vdd = V, Vdd = V, LSL = dbm, Nominal =. dbm Notes:. Data sample size is samples taken from different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.. Measurements are made on production test board which represents a trade-off between optimal Gain, NF, OIP and OPdB. Circuit losses have been de-embedded from actual measurements.

4 Demo Board Layout Demo Board Schematic IN VBias GND VDD GND VDD Rb Ra R C C R Cb C Ca L Ca Cb R C R C C C OUT C L C L C L L C GND AVAGO JAN Technologies RFIN C C C R L R R C C L C Qbias Vdd Q R Q Vdd C C C L C RFOUT MANGROVE Figure. Demo Board layout diagram. Figure. Demo Board schematic diagram. Recommended PCB material is mils Rogers R. Suggested component values may vary according to layout and PCB material. Table. Component list for MHz matching Part Size Value Detail Part Number Notes C, C pf (Murata) GRMCHJDE DC Blocking Capacitors C pf (Murata) MCHAJK DC Blocking Capacitor C pf (Murata) GRMCHJZE Bypass Capacitor C.uF (Murata) GRMRAKAD Bypass Capacitor Ca.uF (Murata) GRMRAKED Bypass Capacitor C pf (Murata) GRMCHJZE Bypass Capacitor Ca, Cb N/A Not used Not used Bypass Capacitor C, C.uF (Murata) GRMREME Bypass Capacitors L nh (Toko) LL-FHLNJ Input Match for NF L nh (Toko) LL-FHLNJ Output match for Q L nh (Toko) LL-FHLNJ Output match for Q R, R ohm (Koa) RKZELTP Bridging Resistors R ohm (Rohm) MCRJ Stabilizing Resistor for Q Rb.K ohm (Koa) RMBEJ Biasing Resistor for Q

5 MGA- Typical Performance in Demoboard for MHz T A =, V dd =. V, V dd =. V, I dd = ma, I dd = ma... NF (db). Gain (db)... Frequency (MHz) Figure. NF vs Frequency and Temperature Frequency (MHz) Figure. Gain vs Frequency and Temperature OIP (dbm) Frequency (MHz) Figure. OIP vs Frequency and Temperature OPdB (dbm) Frequency (MHz) Figure. OPdB vs Frequency and Temperature IRL, ORL, Gain, Rev Isol (db) - - S S S S - Frequency (GHz) Figure. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation vs Frequency K - factor Frequency (GHz) Figure. K-factor vs Frequency and Temperature

6 MGA- Typical Performance in Demoboard for MHz T A =, V dd =. V, V dd =. V, I dd = ma, I dd = ma - - IRL (db) - - ORL (db) Frequency (GHz) Figure. IRL vs Frequency and Temperature Frequency (GHz) Figure. ORL vs Frequency and Temperature Idd (ma) Idd (ma) Vdd (V) Figure. Idd vs Vdd and Temperature Vdd (V) Figure. Idd vs Vdd and Temperature OIP (dbm) Pout (dbm) Figure. OIP vs Output Power and Temperature at MHz

7 MGA- Q Typical Scattering Parameters, Vdd = V, Idd = ma Freq S S S S GHz Mag. Ang. Mag. Ang. Mag. Ang. Mag. Ang RF output Reference Plane MGA- Q Typical Noise Parameters, Vdd = V, Idd = ma Freq GHz Fmin db Γopt Mag. Γopt Ang. Rn/ RF input Reference Plane bias LNA LNA Figure. Notes: Measurements are made on mils Rogers R TRL Board. Figure shows the input and output reference plane for Q.

8 MGA- Q Typical Scattering Parameters, Vdd = V, Idd = ma Freq S S S S GHz Mag. Ang. Mag. Ang. Mag. Ang. Mag. Ang RF input Reference Plane MGA- Q Typical Noise Parameters, Vdd = V, Idd = ma Freq GHz Fmin db opt Mag. opt Ang. Rn/ bias LNA LNA RF output Reference Plane Figure. Notes: Measurements are made on mils Rogers R TRL Board. Figure shows the input and output reference plane for Q.

9 Package Dimensions Pin Dot By marking. ±.. ±. AVAGO YYWW XXXX. Ref.. ±.. ±.. Bsc. ±. Exp.DAP PIN # IDENTIFICATION CHAMFER. x. ±. Exp.DAP... ±.. Ref. TOP VIEW SIDE VIEW BOTTOM VIEW PCB Land Patterns and Stencil Design LAND PATTERN STENCIL OPENING Notes:. All dimensions are in milimeters.. mil stencil thickness recommended... COMBINATION OF LAND PATTERN & STENCIL OPENING

10 Device Orientation REEL USER FEED DIRECTION CARRIER TAPE AVAGO YYWW XXXX AVAGO YYWW XXXX AVAGO YYWW XXXX USER FEED DIRECTION COVER TAPE TOP VIEW END VIEW Tape Dimensions. ±.. ±.. ±. Ø. ±.. ±.. ±... ±. Ø. ±.. ±. MAX MAX. ±.. ±.. ±. A. K. B. Part Number Ordering Information Part Number No. of Devices Container MGA--TRG Reel MGA--BLKG antistatic bag

11 Reel Dimensions ( inch reel) SEE DETAIL "X" SLOT HOLE "b".mm EMBOSSED LETTERS LETTERING THICKNESS:.mm SLOT HOLE "a" Ø.±. FRONT BACK PS SLOT HOLE(x) APART. PS RECYCLE LOGO FRONT VIEW SLOT HOLE "a":.±.mm(x) SLOT HOLE "b":.±.mm(x) R. +.*. -.. MIN. +. Ø. -. Ø. MIN. R. FRONT BACK DETAIL "X" Ø.±. Ø.±.. DETAIL "Y" (Slot Hole). EMBOSSED RIBS RAISED:.mm, WIDTH:.mm BACK VIEW Ø.±. Ø.±. SEE DETAIL "Y".* MAX. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright - Avago Technologies. All rights reserved. AV-EN - December,