Application Note 5421

Transcription

1 MGA GHz W-CDMA Driver Amplifier Design using Avago Technologies MGA Application Note 5421 Introduction Avago Technologies MGA is high linearity, 0.25Watt (24dBm) driver amplifier designed for 250MHz to 3GHz frequency band operation. MGA is housed in a standard SOT-89 package which is the industrial preferred package for low power driver amplifier. This device features excellent input and output return loss that is achieved through internal input match and output pre-match circuits. This reduces the number of external components and the complexity of the manufacturing process. With its competitive Third-Order Output Intercept Point (OIP3), Small Signal Gain and 1-dB Output Power Compression (P1dB), MGA is well suited for W-CDMA driver amplifier application. This application note will describe the use of MGA as a driver amplifier in W-CDMA 1.92 ~ 1.98GHz uplink band tuned for optimum OIP3. Pin Configuration, Internal Biasing and Circuit Description Figure 1a and 1b is the MGA package s top and bottom view, while Figure 1c is the MGA typical application circuit. The integrated bias simplifies the external biasing circuitry of MGA that allows designers to focus on the output matching design. When possible, biasing through the matching network will often minimize the number of components. As for MGA-30489, bias-decoupling and output matching network is combined and designed using 3 elements network consist of one inductor, L1 and two capacitors, C1 and C8. Besides matching, C7 and C8 capacitors are also behave as RF coupling capacitors for the intended frequency and at the same time as a DC blocking capacitors. C2 and C3 are the decoupling capacitors to bypass any unwanted low frequency noise from DC supply. S S 30X G S D D S G Figure 1a. MGA Top View Figure 1b. MGA Bottom View Figure 1c. MGA Generic Application Circuit

2 Demoboard and 50Ω Transmission Line Design Figure 2 shows the MGA demoboard s cross section. The demoboard is 3 layers PCB with 0.5 ounce (oz) of copper (Cu) on each layer and equipped with 10mils (0.25mm) Rogers RO4350 as a dielectric material. FR-4 material is added to the PCB structure for mechanical strength. The FR-4 layer also contributes to the overall demoboard thickness of 62mils (1.57mm) which suits most of the standard edge-mounted SMA connector. Both RF input and output traces are using microstrip transmission line with Z 0 = 50Ω. A non-50ω traces may degrade board performance especially on the return loss. With 10mils of dielectric thickness and 0.7mils of microstrip thickness (0.5oz of Cu), the width of microstrip line is designed to be 22mils (0.56mm) to achieve 50Ω of Z 0 and suits for the edge-mounted SMA connector center pin. All the microstrip design and calculation were done using AppCAD, free and handy software from Avago Technologies. ( docs/6001) Figure 3 is the snapshot of AppCAD microstrip design windows for MGA Tuning for Optimum OIP3 As described earlier, MGA output is pre-matched and this gives the designers the flexibility to design accordingly to suit the required specification and applications. In order to demonstrate this capability, the output matching network was evaluated at 1.92 to 1.98GHz W-CDMA uplink band, using the board shown in Figure 18 and the following discussion will emphasize on the tuning and effect of the output matching network to the OIP3 performance since it is one of the linearity figure of merits. 0.5 Oz Cu (0.7 mils) R04350 (10 mils) 0.5 Oz Cu (0.7 mils) FR4 (50 mils) 62 mil 0.5 Oz Cu (0.7 mils) Figure 2. Demoboard PCB Stacking Structure Figure 3. Microstrip Design using AppCAD Software 2

3 Small Signal Performance and Stability Factor Return Loss (db) IRL ORL -30 Figure 4. Return Loss Gain (db) Small Signal Gain Reverse Isolation Figure 5. Gain and Isolation Reverse Isolation (db) Noise Figure (db) Figure 6. Noise Figure Rollet Stability Factor, K Rollet Stability Factor, K 30 Small Signal Gain Figure 7. Wideband Gain Sweep and K-Factor Small Signal Gain (db) The demoboard performance was measured under the following test conditions: Vdd = 5.0 V, Id = 100 ma and Fc = 1.92 ~ 1.98GHz. As shown in Figure 4, both input return loss (IRL) and output return loss (ORL) are better than -14 db. The demoboard demonstrated a gain variation less than 0.5 db across the W-CDMA uplink operating range as can be seen from Figure 5. In transmitter line-up, the pass-band gain variation or ripple in driver amplifier stage will affect the overall gain flatness. As a driver amplifier, Reverse Isolation (S12) is not critical parameters as compared to the Power Amplifier (PA). Reverse isolation of -25dB is sufficient to prevent any VSWR change on the following section [1]. The in-band noise figure is less than 3.5 db which is suitable for most driver amplifier requirement. The demoboard is unconditionally stable (K 1) from DC to 20 GHz as shown in Figure 7. In addition, there is no abnormal gain peak or slump in the wideband frequency response that may cause instability in critical conditions (e.g. when the amplifier is brought closer to a metal material that coincides with the gain peak). 3

4 OIP3 and P1dB Performance OIP3 (dbm) Figure 8. OIP3 across the band OP1dB (db) Figure 9. OP1dB across the band Gain (db)and Output Power (dbm) Output Power 40 Gain 28 PAE Input Power (dbm) Figure 10. Gain, Output Power and PAE over Input Power PAE (%) With 10MHz frequency spacing and -10dBm/tone, the two-tone test for MGA exhibits 39dBm of OIP3 as shown in Figure 8. Referring to the output, the demoboard is able to produce 23dBm of P1-dB as illustrated in Figure 9. Return Loss Improvement With pre-matched output matching design, the input and output return loss can be improved with the trade-off on OIP3 performance. Designing the amplifier s input and output for a close match to 50Ω over the operating bandwidth will prevent any unpredictable shift in the frequency response. In attempt to get the best return loss, output matching network (L1, C1 and C8) is conjugately matched. The schematic and BOM for this tuning are shown in Figure 20 and Table 1. 4

5 -10 L Figure 11. Gamma Load (ΓL) location for 1.9GHz Input Return Loss (db) Figure 12. Input Return Loss Improvement Output Return Loss (db) Figure 13. Output Return Loss Improvement OP1dB (dbm) Figure 14. OP1dB Comparison OIP3 (dbm) Figure 15. OIP3 Comparison Rollet Stability Factor, K Figure 16. K-Factor Comparison K=1 5

6 Due to the FET characteristic, Gamma Load (Γ L ) for optimum OIP3 location and 50Ω point are located apart from each other. Moving the Γ L further from IP3 optimum point towards 50Ω will degrade the OIP3 performance as shown in Figure 11. As illustrated in Figure 12 to Figure 15, conjugate match will improve the return loss however; at the same time deteriorate the OIP3 performance by 2dB from the typical 39dBm of optimum OIP3. A proper conjugate matching design will improve both input and output return loss by 4dB while the small signal gain is preserved at approximately 13dB and OP1dB of +23dBm. As the demoboard is unconditionally stable (k>1), then this application circuit is stable for all possible source and load terminations. Schematic, Component Placement and Bill of Material Figure 17. Demoboard Top View Figure 18. Demoboard Bottom View Figure 19. Schematic for Best OIP3 Figure 20. Schematic for Best Return Loss The excess component pads, reference designators, supply lines and traces in the demoboard as shown in Figure 17 are purposely designed for Avago s SOT-89 general purpose board. On top of that, this layout design provides design and tuning flexibility to customize MGA s external circuitry to suit the intended needs and applications. 6

7 Table 1. Bill of Materials Ref. Designator Value Best OIP3 Value Best RL Manufacturer & Series Description C1 2.7pF 8.2pF Murata GRM1555C Output Matching/RF Bypass C2 0.1uF 0.1uF Murata GRM1555C DC Bypass Capacitor C3 2.2uF 2.2uF Murata GRM1888C DC Bypass Capacitor C7 100pF 22pF Murata GRM1555C Blocking Capacitor/Input Matching C8 100pF 8.2pF Murata GRM1555C Blocking Capacitor/Output Matching L1 3.3nH 47nH TOKO LL1005-FHL Output Matching/RF Choke MGA Performance Summary High linearity, housed in industrial preferred package, integrated bias and input matching are the key features besides the evaluation test results that ensure the MGA s suitability as driver amplifier in W-CDMA 1.92 ~ 1.98GHz uplink band. Table 2. MGA Performance Summary Parameters* Tuned for Best Return Loss Unit Supply Voltage, Vdd V Board Total Current, Idd ma Input Return Loss, S db Output Return Loss, S db Small Signal Gain, S db Reverse Isolation, S db Output Third-Order Intercept Point, OIP3* dbm Output 1-dB Gain Compression Point, OP1dB dbm Noise Figure, NF db Rollet Stability Factor, K > 1 > 1 * fspacing = 10MHz; Pin = -10dBm/tone Reference 1. MGA-30316, ½W High Linearity Power Amplifier (3.3GHz ~ 3.9GHz), Application Notes 5353, Avago Technologies. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV EN - April 22, 2009