Application Note 1373

Transcription

1 ATF-511P8 900 MHz High Linearity Amplifier Application Note 1373 Introduction Avago s ATF-511P8 is an enhancement mode PHEMT designed for high linearity and medium power applications. With an OIP3 of 41 dbm and a 1 db compression point of 25 dbm, the ATF-511P8 is well suited as a base station transmit driver or a first or second stage LNA in a receive chain. Whether the design is for a W-CDMA, CDMA, or GSM basestation, this device delivers good linearity in the form of OIP3 or ACLR, which is required for standards with high peak to average ratios. Application Guidelines The ATF-511P8 device operates as a normal FET requiring both input and output matching as well as DC biasing, but unlike a depletion mode transistor, this enhancement mode device only requires a single positive power supply. This means a positive voltage is placed on the drain and on the gate in order for this transistor to turn on. This application note walks through the RF and DC design employed in a single FET amplifier. Included in this description is an active feedback scheme to accomplish this DC biasing. RF Input & Output Matching In order to achieve maximum linearity, the appropriate input (Γ s ) and output (Γ L ) impedances must be presented to the device. Correctly matching from these impedances to 50Ωs will result in maximum linearity. Although ATF-511P8 may be used in any other impedance system, data collected for this data sheet is all referenced to a 50Ω system. The input load pull parameter at 900 MHz is shown below in Figure 1 along with the optimum S11 conjugate match. Thus, it should be obvious from this illustration that if this device is matched for maximum Return Loss i.e. S11*, then OIP3 will be sacrificed. Conversely, if ATF-511P8 is matched for maximum linearity, then Return Loss will not be greater than 10 db. For most applications a designer will require VSWR greater than 2:1, hence limiting the input match close to S11*. Proceeding from the same premise, the output match of this device becomes much simpler. As background information, it is important to note that OIP3 is largely dependant on the output match and that output Return Loss is also required to be greater than 10 db. So, Figure 2 shows how both good output return loss and good linearity can be achieved simultaneously with the same impedance point. Of course, these points are valid only at 900 MHz, and other frequencies will follow the same design rules but will have different locations. Also, the location of these points is largely due to the manufacturing process and partly due to IC layout but in either case beyond the scope of this application note. S22* ΓL ΓS Figure 2. Output Match for ATF-511P8 at 900 MHz. S11* Figure 1. Input Match for ATF-511P8 at 900 MHz.

2 Once a designer has chosen the proper input and output impedance points, the next step is to choose the correct topology to accomplish this match. For example to perform the above output impedance transformation from 50Ω to the given load parameter of , two possible solutions exist. The first potential match is a high pass configuration accomplished by a shunt inductor and a series capacitor shown in Figure 3 along with its frequency response in Figure 4. Figure 3. High Pass Circuit. Amp Frequency Figure 4. High Pass Frequency Response. The second solution is a low pass configuration with a shunt capacitor and a series inductor shown in Figures 5 and 6. RF in L1 C1 Figure 5. Low Pass Circuit. Amp RF out this example the input and output match both essentially function as high pass filters, but the high frequency gain of the device rolls off precipitously giving a narrow band frequency response, yet still wide enough to accommodate a GSM 900 MHz or 850 MHz transmit bands. For more information on RF matching techniques refer to MGA Data Sheet[1]. Active Bias [3] Due to very high DC power dissipation and small package constraints, it is recommended that the ATF-511P8 use active biasing. The main advantage of an active biasing scheme is the ability to hold the drain to source current constant over a wide range of temperature variations. A very inexpensive method of accomplishing this is to use two PNP bipolar transistors arranged in a current mirror configuration as shown in Figure 7. Due to resistors R1 and R3 this circuit is not acting as a true current mirror, but if the voltage drops across R1 and R3 are kept identical, the current through R3 is stabilized and therefore Ids and Vds are also kept stable. Transistor Q1 is configured with its base and collector tied together. This acts as a simple PN junction, which helps temperature compensate the Emitter-Base junction of Q2. To calculate the values of R1, R2, R3, and R4 the following parameters must be known or chosen first: I ds is the device drain-to-source current. I R is the Reference current for active bias. V dd is the power supply voltage available. V ds is the device drain-to-source voltage. V g is the typical gate bias. V be1 is the typical Base-Emitter turn on voltage for Q1 & Q2. Therefore, resistor R3, which sets the desired device drain current, is calculated as follows: Frequency Figure 6. Low Pass Frequency Response. The actual values of these components may be calculated by hand on a Smith Chart or more accurately done on simulation software such as ADS. There are some advantages and disadvantages of choosing a high pass versus a low pass. For instance a high pass circuit cuts off low frequency gain, which narrows the usable bandwidth of the amplifier, but consequently helps avoid potential low frequency instability problems. A low pass match offers a much broader frequency response, but it has two major disadvantages. First it has the potential for low frequency instability, and second it creates the need for an extra DC blocking capacitor on the input in order to isolate the device gate from the preceding stages. Figure 7 displays the input and output matching selected for ATF-511P8. In R3 = V dd V ds' I ds + I c2 (1) where, I C2 is chosen for stability to be 10 times the typical gate current and also equal to the reference current I R. The next three equations are used to calculate the rest of the biasing resistors for Figure 7. R1 = V dd V ds' (2) I R Note that the voltage drop across R1 must be set equal to voltage drop across R3, but with a current of I R. R2 = V ds' V be1 I R (3) R2 sets the bias current through Q1.

3 R2 Q1 VE R1 Vdd R4 Vg Q2 Vds' R3 C6 C4 C5 C3 R5 R6 C8 RFin C1 L2 Q PL Vds L3 C2 RF out L1 ATF-511P8 L4 R7 Figure 7. Active Bias Layout. R4 = V g I C2 (4) R4 sets the gate voltage for ATF 511P8. Ic2=Ie2 assuming the hfe of the PNP transistors is high. Thus by forcing the emitter voltage (V E ) of transistor Q1 equal to V ds, this circuit regulates the drain current similar to a current mirror. As long as Q2 operates in the forward active mode, this holds true. In other words the Collector- Base junction of Q2 must be kept reverse biased. Table 1. Bill of Materials. C1=6.8 pf 0402 Chip Capacitor C2=6.8 pf 0402 Chip Capacitor C3=10 pf 0402 Chip Capacitor C4, C5=0.1 µf 0603 Chip Capacitor C6=1 µf 0805 Chip Capacitor C8=15 pf 0402 Chip Capacitor L1=3.3 nh TOKO LL1005-FH3N3S L2=3.9 nh TOKO LL1005-FH3N9 L3=47 nh TOKO LL1608-FS47 L4=4.7 nh TOKO LL1005-FH4N7S R1=30.1Ω R2=402Ω R3=1.43Ω R4=51.1Ω R5=10Ω R6=1.2Ω R7=4.7Ω Q1, Q2 BCV62C Q3 ATF-511P8

4 PCB Layout A recommended PCB pad layout for the Leadless Plastic Chip Carrier (LPCC) package used by the ATF-511P8 is shown in Figure 8. This layout provides plenty of plated through hole vias for good thermal and RF grounding. It also provides a good transition from microstrip to the device package. For more detailed dimensions refer to pages 13 and 14 of the ATF 511P8 data sheet. High Linearity Tx Driver The need for higher data rates and increased voice capacity gave rise to a new third generation standard know as EDGE. This new standard requires higher performance from radio components such as higher dynamic range and better linearity. This application example presents a highly linear transmit drive for use in the 900 MHz frequency range. Using the RF matching techniques described earlier, ATF-511P8 is matched to the input and output impedances shown in Figure 10. As described previously the input impedance must be matched to S11* in order guarantee return loss greater than 10 db. A high pass network is chosen for this match. The output is matched to Γ L with another high pass network. Figure 8. Microstripline Layout. RF Grounding Unlike SOT packages, ATF-511P8 is housed in a leadless package with the die mounted directly to the lead frame or the belly of the package shown in Figure 9. Pin 8 Drain 7 Pin 6 Pin 5 Source 1 Gate 2 Pin 3 Source 4 Bottom View Figure 9. LPCC Package for ATF-511P8. This simplifies RF grounding by reducing the amount of inductance from the source to ground. It is also recommended to ground pins 1 and 4 since they are also connected to the device source. Pins 3, 5, 6, and 8 are not connected, but may be used to help dissipate heat from the package or for better alignment when soldering the device. This three-layer board contains a 10 mil layer and a 52 mil layer separated by a ground plane. The first layer is Getek RG200D material with dielectric constant of 3.8. The second layer is for mechanical rigidity and consists of FR4 with dielectric constant of 4.2. The next step is to choose the proper DC biasing conditions. From the data sheet, ATF-511P8 produces good linearity at a drain current of 200 ma and a drain to source voltage of 4.5V. Thus to construct the active bias circuit described, the following parameters are given. Ids = 200 ma I R = 10 ma V dd = 5V V ds = 4.5V V g =.51V V be1 =.65V V ds' = 4.7V Using equations 1, 2, 3 and 4, the biasing resistor values are calculated in column 2 of Table 2, and the actual values used are listed in column 3. Vds' is used due to voltage drop across R6. Table 2. Resistors for Active Bias. Resistor Calculated Actual R1 30Ω 30.1Ω R2 405Ω 402Ω R3 1.43Ω 1.43Ω R4 51Ω 51.1Ω 50 Ohm Input Match 1PL Output Match 50 Ohm S11* =.93/ -177 Γ L =.55/ -178 Figure 10. ATF-511P8 Matching.

5 So, the entire circuit schematic for a 900 MHz Tx driver amplifier is shown in Figure 7. Capacitors C4 and C5 are added as a low frequency bypass. These terminate 2nd order harmonics and help improve linearity. Resistors R5 and R6 also help terminate low frequencies, but can prevent resonant frequencies between the two bypass capacitors. Performance of ATF-511P8 at 900 MHz ATF-511P8 delivers excellent performance in the 900 MHz frequency band. With a drain-to-source voltage of 4.5V and a drain current of 200 ma, this device has 18.4 db of gain and 3.1 db of noise figure as shown in Figure 11. Input and output return loss are both greater than 10 db. Although somewhat narrowband, the response is adequate in the frequency range of 850 MHz to 900 MHz, as shown in Figure 12. Thermal Design When working with medium to high power FET devices, thermal dissipation should be a large part of the design. This is done to ensure that for a given ambient temperature the transistor s channel does not exceed the maximum rating, T CH, on the data sheet. For example, ATF 511P8 has a maximum channel temperature of 150 C and a channel to board thermal resistance of 33 C/W, thus the entire thermal design hinges from these key data points. The question that must be answered is whether this device can operate in a typical environment with ambient temperature fluctuations from -25 C to 85 C. From Figure 13 a very useful equation is derived to calculate the temperature of the channel for a given ambient temperature. All these calculations are incorporated into Avago Technologies AppCAD. Hence very similar to Ohms Law, the temperature of the channel is calculated with equation 5 below. T CH = Pdiss (θ ch b + θ b s + θ s a ) + T amb (5) If no heat sink is used or heat sinking is incorporated into the PCB board, then equation 5 may be reduced to: T CH = Pdiss (θ ch b + θ b a ) + T amb (6) where, θ b-a is the board to ambient thermal resistance. θ ch-b is the channel to board thermal resistance. GAIN, db Figure 11. Measured Gain and Noise Figure vs. Frequency. INPUT AND OUTPUT RETURN LOSS, db Figure 13. Thermal Resistance Definitions. Gain Noise Figure FREQUENCY, GHz FREQUENCY, GHz Figure 12. Measured Input and Output Return Loss vs. Frequency. Pdiss=Vds x Ids θ ch-b θ b-s θ s-a Tch (channel) Tb (board or belly of the part) Ts (sink) Ta (ambient) Input RL Output RL NOISE FIGURE, db 5

6 The board to ambient thermal resistance thus becomes very important for this is the designer s major source of heat control. To demonstrate the influence of θ b-a, thermal resistance is measured for two very different scenarios using the ATF-511P8 demoboard. The first case is the ATF demoboard mounted on a chassis or metal casing. The second case is just the demoboard with no heat sink; the results are given below: Calculating the temperature of the channel for these two scenarios gives a good indication of what type of heat sinking is needed. Case 1: chassis mounted with fan at 85 C Tch = P x (θ ch-b +θ b-a ) + Ta =.9W x (33+3) C/W + 85 C Tch = 117 C Figure 14. RF Layout for Demo Board. Case 2: no heat sink Tch = P x (θ ch-b +θ b-a ) + Ta =.9W x ( ) C/W +85 C Tch = 144 C In other words if the board is mounted to a chassis, the channel temperature is guaranteed to be 117 C, safely below the 150 C maximum. But on the other hand, if no heat sinking is used and the θ b-a is above 27 C/W (32.9 C/W in this case), then caution must be used so the channel temperature does not exceed 150 C. Thus, for reliable operation of ATF-511P8 and extended MTBF, it is recommended to use some form of thermal heat-sinking. This may include any or all of the following suggestions: Maximize vias underneath and around package. Maximize exposed surface metal. Use 1 oz or greater copper clad. Minimize board thickness. Metal heat sinks or extrusions. Fans. Mount PCB to Chassis. Application Note 1327 gives a detailed table of comparison of various materials recommended for heat-sinking. Figure 15. Assembly Drawing for Active Bias Circuit. Summary A high linearity Tx driver amplifier for GSM850 and GSM900 has been presented and designed using Avago s ATF-511P8. This includes RF, DC and good thermal dissipation practices for reliable lifetime operation. A summary of results at 900 MHz is given by: Gain = 18.4 db OIP3 = 41.2 dbm P1dB = 25.0 dbm NF = 3.1 db

7 References [1] MGA High Linear Amplifier Data Sheet, Available from: < [2] Ward, A. (2001) Avago ATF Low Noise Enh a n c e m e n t M o d e Ps e u d o m o r p h i c H E M T i n a Surface Mount Plastic Package, 2001 [Internet], Available from: < [Accessed 22 August, 2002]. [3] Biasing Circuits and Considerations for GaAs MESFET Power Amplifiers, 2001 [Internet], Available from: < [Accessed 22 August, 2002] [4] Saul Espino. (2003) Application Note 1327: High Linearity and Medium Power Applications using the Avago ATF-511P8 PHEMT Avago Eesof Advanced Design System (ADS) electronic design automation (EDA) software for system, RF, and DSP designers who develop communications products. More information about Avago EDA software may be found on: Performance data for Avago ATF-511P8 may be found on For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright 2008 Avago Technologies Limited. All rights reserved. Obsoletes EN AV EN - January 19, 2008