Data Sheet. ALM GHz GPS Low Noise Amplifier with Integrated Filter and Variable Current/Shutdown Function. Features.

Transcription

1 LM GHz GPS Low Noise mplifier with Integrated Filter and Variable Current/Shutdown Function Data Sheet Description vago Technologies LM-141 is an LN module, with integrated filter, designed for GPS band applications at 1.575GHz. The LN uses vago Technologies proprietary Gas Enhancement-mode phemt process to achieve high gain with very low noise figure and high linearity. Noise figure distribution is very tightly controlled. CMOS-compatible shutdown pin is included either for turning the LN on/off, or for current adjustment. The integrated filter utilizes an vago Technologies leadingedge FBR filter for exceptional rejection at Cell/PCS- Band frequencies. The LM-141 is useable down to 1 V operation. It achieves low noise figure, high gain and linearity even at 1 V, making it suitable for use in critical low-power GPS applications or during low-battery situations. pplication GPS Band LN Component Image SURFCE MOUNT 3.3 x.1 x 1.1 mm3 1-Lead MCOB RF_IN 1 Gnd SD 3 Gnd 9 FILTER-OUT Gnd 7 TOP VIEW BOTTOM VIEW Note: Package marking provides orientation and identification 141 = Product Code YY = Year of manufacture WW = Work Week of manufacture 1 VDD Gnd 4 10 Gnd Gnd 11 Gnd Gnd 5 10 Gnd 141 WWYY 11 Gnd Gnd 5 Gnd 1 VDD Gnd 4 9 Gnd FILTER-OUT 7 Gnd 1 RF_IN Gnd 3 SD Features Very Low Noise Figure: 0. db typical High Gain: 13.5 db typical High IIP3 and IP1dB Exceptional Cell/PCS-Band rejection dvanced Gas E-pHEMT Technology Low external component count Wide Supply Voltage: 1 V to 3. V Shutdown current: < 0.1 µ CMOS compatible shutdown pin (SD) V: 0.1 m djustable current via single external resistor/voltage Meets MSL3 and Lead-Free ESD-protected RF input: 3 kv HBM Small package dimension: 3.3(L)x.1(W)x1.1(H) mm 3 Specifications (Typical Performance at 5 C) t GHz, Vdd =.5 V, Idd =.0 m Gain = 13.5 db NF = 0. db IIP3 = +7.0 dbm, IP1dB = +.7 dbm S11 = -.4 db, S = -1.3 db Cell-Band Rejection: 54 dbc PCS-Band Rejection: 3 dbc t GHz, 1.0 V supply S1 =. db NF = 1. db Idd = 1.9 m ttention: Observe precautions for handling electrostatic sensitive devices. For RF_IN (Pin 1): ESD Human Body Model = 3 kv ll other pins: ESD Machine Model = 40 V ESD Human Body Model = 300 V Refer to vago Technologies pplication Note 004R: Electrostatic Discharge, Damage and Control

2 bsolute Maximum Rating [1] T = 5 C Symbol Parameter Units bsolute Max. Vdd Device Drain to Source Voltage [] V 3. Idd Drain Current [] m 0 P in,max CW RF Input Power (Vdd =.5 V, Idd = 9.0 m) dbm 15 P diss Total Power Dissipation [4] mw 7 Tj Junction Temperature C 150 T STG Storage Temperature C -5 to 150 Thermal Resistance [3] (Vdd =.5 V, Idd = 9 m), qjc = 35. C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage.. ssuming DC quiescent conditions. 3. Thermal resistance measured using Infra-Red measurement technique. 4. Board (module belly) temperature T B is 5 C. Derate.4 mw/ C for TB > 15 C. Product Consistency Distribution Charts [5, ] Figure 1. Gain at GHz; LSL = 11.0 db, nominal = 13.5 db Figure. NF at GHz; nominal = 0. db, USL = 1. db Figure 3. Idd at GHz; nominal =.0m, USL = 15 m Figure 4. Cell Band Rejection at 7.5 MHz relative to GHz; nominal = 54 dbc, LSL = 45 dbc Figure 5. PCS Band Rejection at 15 MHz relative to GHz; nominal = 3 dbc, LSL = 45 dbc Notes: 5. Distribution data sample size is 000 samples taken from different LN wafer lots and 3 different filter wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.. Measurements are made on a production test board, which represents a trade-off between optimal Gain, NF, IIP3, IP1dB, VSWR, Cell Band and PCS Band Rejection. Circuit trace losses have not been de-embedded from actual measurements

3 Electrical Specifications T = 5 C, Vdd = +.5V, Vsd = +.V, Idd = m (typ), R = 10 kω, Freq = 1.575GHz - Typical Performance [] unless otherwise specified. Table 1. Performance Table at Nominal Operating Conditions Symbol Parameter and Test Condition Units Min. Typ Max. G Gain db NF [7] Noise Figure db IP1dB Input 1 db Compressed Power dbm IIP3 [9] Input 3rd Order Intercept Point fc ±.5 MHz) dbm S11 Input Return Loss db S Output Return Loss db S1 Reverse Isolation db Cell Band Rejection Relative to MHz dbc PCS Band Rejection Relative to MHz dbc Idd Supply DC current at Shutdown (SD) Voltage Vsd =. V m Ish Shutdown Vsd = 0 V µ T = 5 C, Vdd = +.5V, Vsd = +1.V, Idd = 4.5m (typ), R = 10 kω, Freq = 1.575GHz - Typical Performance [] unless otherwise specified. Table. Typical Performance at Vdd = +.5V, Vsd = +1.V, Idd = 4.5m (typ) Symbol Parameter and Test Condition Units Typ. G Gain db 1. NF [7] Noise Figure db 0.94 IP1dB Input 1 db Compressed Power dbm 4.5 IIP3 [9] Input 3rd Order Intercept Point fc ±.5 MHz) dbm 5.7 S11 Input Return Loss db -7 S Output Return Loss db -10. S1 Reverse Isolation db -. Cell Band Rejection Relative to MHz dbc 55 PCS Band Rejection Relative to MHz dbc 1 Idd Supply DC Current at Shutdown (SD) Voltage Vsd = 1. V m 4.5 Ish Shutdown Vsd = 0 V µ 0.1 Notes: 7. For noise figure measurement, input board loss has not been deducted.. Measurements at GHz obtained using demo board described in Figures and GHz IIP3 test condition: FRF1 = MHz, FRF = MHz with input power of -0 dbm per tone measured at the worst case side band. 3

4 Vdd = + V, Vdd = +1.5 V, Vdd = +1 V, Freq = GHz Typical Performance [] (Vsd = Vdd, R = 0 ohms) Table 3. Typical Performance at Low Operating Voltages with R (See Figures and 7) Set to 0 ohms Symbol Parameter and Test Condition Units Vdd = V Vdd = 1.5 V Vdd = 1 V G Gain db NF [7] Noise Figure db IP1dB Input 1 db Compressed Power dbm IIP3 [9] Input 3rd Order Intercept Point fc ±.5 MHz) dbm S11 Input Return Loss db S Output Return Loss db S1 Reverse Isolation db Cell Band Rejection PCS Band Rejection Relative to MHz dbc Relative to MHz dbc Idd Supply DC Current m Ish Shutdown Vsd = 0 V µ Notes: 7. For noise figure measurement, input board loss has not been deducted.. Measurements at GHz obtained using demo board described in Figures and GHz IIP3 test condition: FRF1 = MHz, FRF = MHz with input power of -0 dbm per tone measured at the worst case side band. 4

5 4 3 1 RF input RF output DC Pin Configuration of 4-pin Connector Pins pointing out of the page Pins 1, 4 - GND Pin = Shutdown (SD) Pin 3 = Vdd Supply Circuit Symbol Size Description L1 040 Not Used L 040. nh Inductor (Toko) L nh Inductor (Toko) C µf Capacitor (Murata) C pf Capacitor (Rohm) C pf Capacitor (Rohm) C pf Capacitor (Rohm) R Ohms Resistor (Rohm) R k Ohms Resistor (Rohm) Z1 005 Not Used Figure. Demoboard and application circuit components table 5

6 1, 4 GND 3 Vdd R1 L1 C1 Z1 C L 1 50-Ohms TL L3 1 INPUT MTCH FILTER C9 50-Ohms TL, 4, 5,, 7, 9, 10, 11 3 R MODULE OUTLINE SD C3 Figure 7. Demoboard and application schematic diagram Notes: The demoboard of Figure is Rogers RO4350 with typical Dk=3.4 (@10GHz). L3 and the module s internal input pre-match form the input matching network. The module has built-in DC-blocking capacitors at the input and output. This circuit demonstrates that very low noise figure is obtainable with standard 040 chip inductors instead of high-q wirewound inductors. C and L form a matching network at the output of the LN stage, which can be tuned to optimize gain and return loss. For example, higher gain can be obtained by increasing the value of C but at the expense of stability. Changing the value of L can improve the PCS rejection, but impacts output return loss. L1 is a choke which isolates the demoboard from external disturbances during measurement. It is not needed in actual application. Likewise, C1 and C3 mitigate the effect of external noise pickup on the Vdd and SD lines respectively. These components are not required in actual operation. R1 is a stability-enhancing resistor. C9 is a DC-blocking capacitor. It is also not required in actual operation. Bias control is achieved by either varying the SD voltage (Vsd) with/without R, or fixing the SD voltage to Vdd and adjusting R for the desired current. Typical value for R is 10k Ohms for m total current at Vdd =.5 V and Vsd = +.0 V. For applications where it is more appropriate to have SD (Vsd) connected to Vdd, a 1 k Ohms resistor value for R is suggested (where Vdd =.5 V). For low-voltage operation such as Vdd = 1.5 V or 1.0 V, R may be omitted and SD (Vsd) connected directly to Vdd. The grounding regime for the LM-141 is critical to achieving the PCS- and Cell-Band Rejections shown in Figure 9. Please refer to the PCB Land Patterns section of this document for the exact locations of the grounding vias.

7 LM-141 Typical Performance Curves, Vdd = +.5 V, Vsd = +.V, Idd = m (typ) (at 5 C unless specified otherwise) IRL freq= 1.575GHz db(s(1,1))=-.44 Gain freq= 1.575GHz db(s(,1))= ISO freq= 1.575GHz db(s(1,))=-3.4 ORL freq= 1.575GHz db(s(,))= Gain IRL ORL db(s(,)) db(s(,1)) db(s(1,)) db(s(1,1)) ISO CELL PCS freq, GHz CELL ind Delta= E dep Delta= delta mode ON PCS ind Delta= 3.100E dep Delta= delta mode ON Figure. Typical S-Parameter plot Figure 9. Multiple module plots of rejecton at Cell and PCS Bands 7

8 LM-141 Typical Performance Curves, R = 10 kω (at 5 C unless specified otherwise) GIN (db) m m 11m Figure 10. Gain vs. Vdd vs. Idd NF (db) Figure 11. NF vs. Vdd vs. Idd 5m m 11m IIP3 (dbm) m m 11m IP1dB (dbm) m m 11m Figure 1. IIP3 vs. Vdd vs. Idd Figure 13. IP1dB vs. Vdd vs. Idd 1 10 Idd (m) Vsd (V) Figure 14. Idd vs. Vsd (Vdd =.5 V)

9 LM-141 Typical Performance Curves, R = 10 kω (at 5 C unless specified otherwise) CELL BND REJECTION (dbc) m m 11m PCS BND REJECTION (dbc) m m 11m Figure 15. Cell band rejection vs. Vdd vs. Idd Figure 1. PCS band rejection vs. Vdd vs. Idd 9

10 LM-141 Typical Performance Curves, R = 10 kω (at 5 C unless specified otherwise) GIN (db) Figure 17. Gain vs. Vdd vs. Temp (Idd = m) -40 C 5 C 5 C NF (db) Figure 1. NF vs. Vdd vs. Temp (Idd = m) -40 C 5 C 5 C IIP3 (dbm) Figure 19. IIP3 vs. Vdd vs. Temp (Idd = m) -40 C 5 C 5 C IP1dB (dbm) Figure 0. IP1dB vs. Vdd vs. Temp (Idd = m) -40 C 5 C 5 C CELL BND REJECTION (dbc) C 5 C 5 C PCS BND REJECTION (dbc) C 5 C 45 5 C Figure 1. Cell band rejection vs. Vdd vs. Temp (Idd = m) Figure. PCS band rejection vs. Vdd vs. Temp (Idd = m) 10

11 LM-141 Scattering Parameter and Noise Parameter Measurement R1 L1 C1 REFERENCE PLNE C L REFERENCE PLNE 1 1 INPUT FILTER MTCH 3 R MODULE OUTLINE C3 Figure 3. Scattering and noise parameter reference planes 11

12 LM-141 Typical Scattering Parameters at 5 C, Vdd =.5 V, Vsd = +.V, Idd = m (typ) The S- and Noise Parameters are measured using the PCB described in Figures and 7. The PCB material is 10 mils Rogers RO4350. Figure 3 shows the input and output reference planes. The circuit values, with the exception of L3, are as indicated in Figure. Freq. S11 S11 S1 S1 S1 S1 S1 S S (GHz) Mag. ng. (db) Mag. ng. (db) ng. Mag. ng

13 LM-141 Typical Scattering Parameters at 5 C, Vdd =.5 V, Vsd = +1.V, Idd = 4.5m (typ) Freq. S11 S11 S1 S1 S1 S1 S1 S S (GHz) Mag. ng (db) Mag. ng. (db) ng. Mag. ng

14 LM-141 Typical Noise Parameters at 5 C, Freq = GHz, Vdd =.5 V, Vsd = +.V, Idd = m (typ) Freq Fmin GMM OPT (GHz) (db) Mag ng Rn/ LM-141 Typical Noise Parameters at 5 C, Freq = GHz, Vdd =.5 V, Vsd = +1.V, Idd = 4.5m (typ) Freq Fmin GMM OPT (GHz) (db) Mag ng Rn/ Notes: The exceptional noise figure performance of the LM-141 is due to its highly optimized design. In this regard, the Fmin of the LM- 141 shown above is locked down by the internal input pre-match. This allows the use of relatively inexpensive chip inductors for external matching. The NF performance of the LM-141 is also very resilient to operating conditions. For example, at Idd = 4.5 m, the degradation in NF is only 0.1 db, and not more than 0.15 db degradation over temperature. Part Number Ordering Information Part Number No. of Devices Container LM-141-BLKG 100 ntistatic bag LM-141 -TR1G Reel 14

15 Package Dimensions x 0.9 PIN 1 ORIENTTION LL EDGES GPS x WWYY x ± x 0.35 SQ x ± ± 0.10 x 1.7 7x 0.1 x 0.0 TOP VIEW SIDE VIEW BOTTOM VIEW NOTES: 1. LL DIMENSIONS RE IN MILLIMETERS.. DIMENSIONS RE INCLUSIVE OF PLTING. 3. DIMENSIONS RE EXCLUSIVE OF MOLD FLSH ND METL BURR. PCB Land Patterns and Stencil Design Dimensions are in mm REF REF REF B C E F G D 0.71 B C D x SQ (For B and C) PCB land pattern and suggested grounding vias 0.00 REF. B C D E F G (SQURE) 0.0 x 0.30 mm 0.57 x 0.30 mm x 0.37 mm x 0.49 mm 0.4 x 0.1 mm 0.57 x 0.17 mm B C D Stencil outline drawing 0.00 REF. E F G B C D Combined PCB land pattern and stencil outline 15

16 Device Orientation REEL USER FEED DIRECTION CRRIER TPE 141 WWYY 141 WWYY 141 WWYY ER ED ECTION COVER TPE TOP VIEW END VIEW Tape Dimensions P10 (3) T Y P0 P (1) D0 F B0 5 MX. F (1) W SECTION Y - Y Y X X P1 () D1 K0 0 SECTION X - X REF REF. R 0.5 DETIL REF. R 0.5 REF. R 0.5 NOTES: 1. MESURE FROM CENTER LINE OF SPROCKET HOLE TO CENTER LINE OF POCKET.. MESURE FROM CENTER LINE OF POCKET HOLE TO CENTER LINE OF POCKET. 3. PITCH TOLERNCE FOR SPROCKET HOLE: 10 PITCH CUMULTIVE TOLERNCE IS ± O. mm. 4. LLOWBLE CMBER TO BE 1 mm PER 50 mm IN LENGTH. DIMENSIONS NOTTION MILLIMETERS ± 0.10 B0.40 ± 0.10 K ± 0.10 D ± 0.05 D1 1.0 ± 0.10 P ± 0.10 P1.00 ± 0.10 P.00 ± 0.10 P ± 0.0 E 1.75 ± 0.10 F 5.50 ± 0.10 W 1.00 ± 0.30 T 0.30 ±

17 Reel Dimensions - 13 inch EMBOSSED LETTERING 1.0mm HEIGHT x MIN. 0.4mm THICK DTE CODE 1MM Ø39.0±1.0 HUB Ø100.0±0.5 PS 9 7 CPN MPN EMBOSSED LETTERING 7.5mm HEIGHT EMBOSSED LETTERING 7.5mm HEIGHT +0.5 Ø (MIN.) EMBOSSED LINE (x) 9.0mm LENGTH LINES 147.0mm WY FROM CEMTER POINT FRONT VIEW 1.5(MIN.) ESD LOGO Ø ** * -0.0 Detail "X" PS RECYCLE LOGO SEE DETIL "X" PS Ø100.0±0.5 Ø39.0±1.0 SLOT 5.0±0.5(3x) BCK VIEW R19.0±0.5 Ø1.3±0.5(3x) 1.4 MX.* For product information and a complete list of distributors, please go to our website: vago, vago Technologies, and the logo are trademarks of vago Technologies Limited in the United States and other countries. Data subject to change. Copyright vago Technologies Limited. ll rights reserved. V0-005EN - June 17, 00