MGA Low Noise Amplifier with switchable Bypass/Shutdown Mode in Low Profile Package. Features. Applications. VBias

Transcription

1 MGA Low Noise Amplifier with switchable Bypass/Shutdown Mode in Low Profile Package Data Sheet Description Avago Technologies MGA is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA) with Bypass/ Shutdown mode. The LNA has low noise and high linearity achieved through the use of Avago Technologies proprietary 0.25 m GaAs Enhancement-mode phemt process. The Bypass/Shutdown mode enables the LNA to be bypassed during high input signal power and reduce current consumption. It is housed in a low profile 2.0 x 1.3 x 0.5 mm 3 6-pin Ultra Thin Package. The compact footprint and low profile coupled with low noise, high linearity make the MGA an ideal choice as a low noise amplifier for mobile and CPE receivers in the WiMAX and WLL (2.5 4) GHz band. Component Image 2.0 x 1.3 x 0.5 mm 3 6-lead Ultra Thin Package 65X Pin Configuration Note: Package marking provides orientation and identification 65 = Product Code X = Month Code Features Low current consumption Adjustable bias current Simple matching network Broadband operation (2.5 4) GHz Low Noise Figure Low current consumption in Bypass Mode, <100 A Fully matched to 50 ohm in Bypass Mode High Linearity (LNA and Bypass Mode) Low profile package Typical Performance 3.5 GHz; 3V, 10mA (Typ): 15.3 db Gain 1.05 db Noise Figure +5.7 dbm Input IP3-2.4 dbm Input Power at 1 db gain compression 4.2 db Insertion Loss in Bypass Mode 17 dbm IIP3 in Bypass Mode (Pin = -20 dbm) <100 A current consumption in Bypass mode Pin 1 (Vbias) Pin 6 (Vsd) Applications Pin 2 (RFin) Pin 3 (Gnd) GND Pin 5 (RFOut) Pin 4 (Vdd) Low noise amplifier for WiMAX, Wireless Local Loop. Other ultra low noise applications in the GHz band. TOP VIEW Simplified Schematic Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 50 V ESD Human Body Model = 300 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. VBias RF IN R L 1 2 Bias / 6 Control 5 LNA 3 4 VSD L L C R RF OUT Vdd C

2 Absolute Maximum Rating [1] T A = 25 C Symbol Parameter Units Absolute Maximum V dd Device Voltage, RF Output to Ground V 5 Vbias Control Voltage V (Vdd-0.3) P in,max CW RF Input Power dbm +12 P diss Total Power Dissipation mw 104 T j Junction Temperature C 150 T STG Storage Temperature C -65 to 150 Thermal Resistance Thermal Resistance [2,3] (V dd = 3.0 V, Id = 10 ma), jc = 80 C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red Measurement Technique. 3. Board temperature (T b ) is 25 C, for T b >146 C, derate the device power at 14 mw per C rise in Board (pakcage belly) temperature. Product Consistency Distribution charts [1] LSL USL USL Figure GHz,Vdd 3V; Vbias 2.7 V LSL = 14 db, Nominal = 15.3 db, USL = 17 db Figure GHz,Vdd 3 V; Vbias 2.7 V Nominal = 1.05 db, USL = 1.35 db USL Note: 1. Distribution data sample size is 3000 samples taken from 3 different wafers and 3 different lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. Figure GHz,Vdd 3 V; Vbias 2.7 V Nominal = 10.0 ma, USL = 12.0 ma 2

3 Electrical Specifications [1] T A = 25 C, Vdd =3 V, Vbias = 2.7 V, RF measurement at 3.5 GHz Typical Performance Symbol Parameter and Test Condition Units Min. Typ. Max. LNA Mode performance ( Vdd = 3 V,Vbias = 2.7 V & VSD = 0 V) Idd Bias Current ma Gain Gain db NF Noise Figure db IIP3 Input Third Order Intercept Point dbm +5.7 IP1dB Input Power at 1 db Gain Compression dbm -2.4 S11 Input Return Loss, 50 source db S22 Output Return Loss, 50 load db -11 S12 Reverse Isolation db -24 BYPASS Mode performance ( Vdd = 3 V, Vbias = 0 V & VSD = 0 V) S21 BYPASS Bypass Mode Insertion Loss db 4.2 IIP3 BYPASS Bypass Mode IIP3 (Tested at -20 dbm input Power) dbm 17 Idd BYPASS Bypass Mode Current A 70 Shutdown Mode performance ( Vdd = 3 V,Vbias = 0 V & VSD = 3 V) S21 SHUTDOWN Shutdown Mode Isolation db 17 Idd SHUTDOWN Shutdown Mode Current A 105 Note: GHz IIP3 test condition: F RF1 = 3.5 GHz, F RF2 = GHz with input power of -20 dbm per tone. Table 1. LNA Switch Truth Table Vbias (V) / Vsd (V) Vdd (V) Mode 2.7 / 0 [1] 3 LNA 0 / 0 [2] 3 BYPASS 0 / 3 [3] 3 SHUTDOWN Notes: 1. Device operation in LNA mode if Vbias > 2.2 V and Vsd < 0.5 V. Bias current of LNA can be varied with different values of Vbias for Vbias > 2.2 V. See Fig 5 below. 2. Device operation in BYPASS mode if Vbias < 0.3 V and VSD < 0.5 V. 3. Device is shutdown if Vsd >2.6 V. In SHUTDOWN mode, LNA and internal Bypass switch is turn OFF. SHUTDOWN mode override Vbias voltage setting. Pin 6 (Vsd) is a Pull-Down logic function pin and recommend to ground it if shutdown function is not used in application. 3

4 Demo Board Layout GND Vbias Vsd GND Vdd GND 5 6 GND OCT 2010 Avago Technologies Vbias GND Vsd Vdd GND MIMOSA v2 RF Input R2 RF Output OUT L2 L3 L1 IN R1 C1 C2 Figure 4. Demo Board Layout Diagram Application Notes 1. Performance in a specified frequency band can be optimized by changing component values in the demo board above to suit the application at that frequency. The schematic on page 5 show components used to demonstrate performance at the ( ) GHz band. 2. Pin1 (Vbias pin) voltage in LNA mode can be varied to enable the LNA bias current to be adjusted, refer to next graph: Id (ma) Vbias (V) Figure 5. Id vs Vbias (Vdd = 3 V; Vsd = 0 V). Vbias is varies in this plot. 4

5 Demo Board Schematic for 3.5 GHz application RF IN (Pin 2) 50-Ohms TL V Bias (Pin 1) R2 L1 1 Bias / 6 Control LNA 4 VSD (Pin 6) L2 L3 C1 50-Ohms TL R1 C2 RF OUT (Pin 5) Vdd (Pin 4) Gnd (Pin 3) Figure 6. Demo Board Schematic Diagram Table 2 Typical Components Used For Demo Board In Fig 4 And Schematic Shown In Fig 6. R2 is adjusted for desired current. Component Vendor Size Value L1 Taiyo Yuden nh L2 Taiyo Yuden nh L3 Taiyo Yuden nh C1 Taiyo Yuden pf C2 Murata F R1 ROHM ohm R2 ROHM Kohm MGA Typical Performance (3.5 GHz match) T A = +25 C, V dd = 3 V, I ds = 10 ma (Vbias = 2.7 V), RF measurement at 3.5 GHz, Input Signal = CW unless stated otherwise. db Input Return Loss -40 Output Return Loss Gain -50 Isolation Figure 7. LNA Mode Gain, Input Return Loss, Output Return Loss, Isolation vs Frequency 5

6 LNA Mode Plots (3.5 GHz match); Vdd = 3 V, Vbias = 2.7 V, Vsd = 0 V Gain (db) ma 9 ma ma 11 ma Figure 8. LNA Mode Gain vs Frequency vs Id NF (db) Figure 9. LNA Mode Noise Figure vs Frequency vs Id 8 ma 9 ma 10 ma 11 ma Gain (db) Vbias (V) Figure 10. LNA Mode Gain vs Vbias vs Temperature 25 C 85 C -40 C NF (db) C 85 C -40 C Vbias (V) Figure 11. LNA Noise Figure vs Vbias vs Temperature IP1dB (dbm) Vbias (V) Figure 12. LNA Mode IP1dB vs Vbias vs Temperature 25 C 85 C -40 C IIP3 (dbm) Vbias (V) Figure 13. LNA Mode IIP3 vs Vbias vs Temperature 25 C 85 C -40 C 6

7 LNA Mode Plots (3.5 GHz match); Vdd = 3 V, Vbias = 2.7 V, Vsd = 0 V Figure 14. Edwards-Sinsky Output Stability Factor(Mu) at Vdd = 3 V Figure 15. Edwards-Sinsky Input Stability Factor(Mu ) at Vdd = 3 V Bypass Mode Plots (3.5 GHz match); Vdd = 3 V, Vbias = 0 V, Vsd = 0 V db Input Return Loss -30 Output Return Loss Gain -35 Isolation Figure 16. Bypass Mode Gain, Input Return Loss, Output Return Loss, Isolation vs Frequency Bypass Insertion Loss (db) Figure 17. Bypass Mode Insertion Loss vs Frequency vs Temperature 25 C 85 C -40 C IIP3 (dbm) Figure 18. Bypass Mode IIP3 vs Frequency vs Temperature 25 C 85 C -40 C IIP3 (dbm) Pin (dbm) Figure 19. Bypass Mode IIP3 vs Input Power 7

8 Shutdown Mode Plots (3.5 GHz match); Vdd = 3 V, Vbias = 0 V, Vsd = 3 V db Input Return Loss Output Return Loss -50 Gain Isolation Figure 20. Shutdown Mode Gain, Input Return Loss, Output Return Loss, Isolation vs Frequency Shutdown Isolation (db) Figure 21. Shutdown Mode Isolation vs Frequency vs Temperature 25 C 85 C -40 C Test Circuit For S and Noise parameter measurement [1] (3.5GHz match) Reference plane MGA V Bias R2 1 (Pin 1) Bias / Control 6 VSD (Pin 6) RF IN (Pin 2) 2 5 RF OUT (Pin 5) LNA 3 4 L3 R1 Vdd (Pin 4) C1 C2 Gnd (Pin 3) Note: 1. The measurement is calibrated up to the input (RFin) and output (RFout) pin of the package. Component Vendor Size Value L3 Taiyo Yuden nh C1 Taiyo Yuden pf C2 Murata F R1 ROHM ohm Figure 22. S-parameter and Noise parameter test circuit on demo board 8

9 MGA LNA Mode typical scattering parameters at 25 C, Vdd = 3 V; Vbias = 2.7 V; Vsd = 0 V Frequency S11 S21 S12 S22 (GHz) Mag Angle db Mag Angle db Mag Angle Mag Angle

10 MGA Bypass Mode typical scattering parameters at 25 C, Vdd = 3 V; Vbias = 0 V; Vsd = 0 V Frequency S11 S21 S12 S22 (GHz) Mag Angle db Mag Angle db Mag Angle Mag Angle

11 MGA LNA Mode typical noise parameters at 25 C, Vdd = 3 V; Vbias = 2.7 V; Vsd = 0 V Freq. (GHz) Fmin (db) opt Mag opt Ang Rn/

12 Package Dimensions Pin#1 DOT by Marking Pin#1 Indicator R ± ± ± X TOP VIEW SIDE VIEW BOTTOM VIEW Notes: 1. All dimensions are in milimeters. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash and metal burr. PCB Land Patterns and Stencil Design sq sq sq R LAND PATTERN WITH VIA STENCIL OPENING Top Metal Solder Mask Opening sq sq Notes: 1. All dimension are in mm. 2. Recommend to use standard 4 mils Stencil thickness COMBINED LAND PATTERN & STENCIL OPENING 12

13 Device Orientation REEL USER FEED DIRECTION CARRIER TAPE 65X 65X 65X USER FEED DIRECTION COVER TAPE TOP VIEW END VIEW Tape Dimensions 4.00 ± ±0.05 Ø 1.50 ± ± ± ±0.10 Ø ± MAX. 45 MAX ± ± ± 0.05 Ao Ko Bo (all dimensions in mm) Part Number Ordering Information Part # Qty Container MGA BLKG 100 Antistatic Bag MGA TR1G Reel MGA TR2G Reel 13

14 Reel Dimensions For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV EN - November 15, 2011