Application Note 5438

Transcription

1 Schottky Enhanced PIN Limiter Compact, Low Threshold and Wideband Application Note 5438 Introduction The sharing of sites or towers by multiple transceivers subjects receiver front-end stages to overload from nonsynchronous transmissions via mutual coupling between adjacent aerials. This problem is compounded by the small transistor feature size needed to improve Low Noise Amplifier (LNA) gain and noise performance at microwave frequencies. The smaller devices unfortunately also have lower input overload tolerance. For example, a typical 8 µm GaAs phemt-based LNA has an absolute maximum RF input power rating of 1 dbm [1]. RF limiters placed between the aerials and the LNA stages can reduce overloading from nearby transmitters while allowing weaker distant signals to pass unimpeded to the LNA. The most common limiter configuration is the shuntconnected PIN diode which biases itself, a self-biasing PIN diode limiter, in the presence of large signals. The limiter s popularity lies its minimal part count since the PIN diode performs the dual functions of rectifying the incoming RF signal and then using the rectified current to bias itself to a low effective series resistance, Rd [2]. An inductor completes the loop for the bias current flow while presenting a high impedance path to RF. Choosing a PIN diode with an extremely thin I-layer lowers the input power required to initiate limiting, because the thinnest PIN diode has the lowest Rd at a given bias current [2]. As the I-layer height is not usually specified in the manufacturer s datasheet, the carrier lifetime τ, can be used as an indirect measure of I-layer height; a shorter carrier life time corresponds to a thinner I layer. A self-bias PIN diode limiter based on the very thin I-layer HSMP-482 PIN diode [3] typically begins attenuating the RF signal when the input power exceeds approximately 11 dbm [2]. Unfortunately, some of the most sensitive LNA transistors may already be in danger of non-reversible parametric changes at this power level. A simple and economical modification to reduce the turn-on threshold, P th, uses a Schottky diode to generate the bias current for the PIN diode. Since the Schottky diode has a lower turn-on threshold voltage than the PIN diode, the limiter s P th is lowered by around 1 db. This anti-parallel PIN-Schottky diode topology is known as the Schottky Enhanced PIN Limiter or Detector Driven Limiter. RF input RF input PIN PIN Conventional PIN diode limiter Schottky enhanced limiter Circulating self-bias current shown in red. Schottky Figure 1. Self-biased (top) and Schottky-enhanced (bottom) PIN limiters

2 Design Rationale The primary aim of creating a multichip limiter in a package is to eliminate the effort and time needed to select the correct diodes. There is a confusingly large variety of PIN and Schottky diode types, each type with its own set of characteristics and performance trade-offs that force the designer to be familiar with both PIN and Schottky diode parameters. The secondary goal is to reduce the limiter s part count and PCB footprint by combining Schottky and PIN diode chips into a compact industry-standard SOT-323 package. The limiter s power handling is maximized by using a low thermal resistance, θjc, package with a rating of 15 C/W. Schottky Enhanced PIN Limiter Principle of Operation The Schottky diode rectifies the incoming RF and produces a current, I F, that is proportional to the incident RF power, Pi. The PIN diode, which is connected anti-parallel to the Schottky diode, provides a return path for I F. The PIN diode behaves like a current-controlled resistor with an equivalent junction resistance, R d, that is controlled by I F. PIN diode resistance, R d is given by: W 2 R d = 2µIF t PIN and Schottky Diode Parameters Pertinent to Limiter Applications Due to the PIN diode s R d α W 2 relation, it is desirable to have a very thin I-region typically, in the 1 to 7 µm range [2, 5]. With the resultant low R d, the limiter turns on earlier (lower turn-on threshold, P th ) and attenuates large signals by a greater amount. Different Schottky diode designs optimize either Peak Inverse Voltage, PIV, or the zero bias junction capacitance, C j. The PIV parameter imposes a limit on the maximum signal amplitude that can be handled by the Schottky diode without damage, whereas C j determines both small signal insertion loss and detection sensitivity. A hybrid Schottky construction was chosen for its C j (~.5 pf) and PIV (~15 V) performance compromise. PIN diode Schottky diode Ground vias Where, W is the PIN diode s I-layer height, μ is the ambipolar mobility of electrons and holes, and t is the minority carrier lifetime [4]. At power levels below the Schottky detection threshold, the unbiased PIN diode resistance, R d, is considerably higher than the transmission line characteristic impedance, Z. Therefore the bulk of incident power will pass through the limiter with almost no attenuation, A. Above the Schottky detector threshold RF rectification produces a current that lowers the PIN diode resistance, R d. The limiter has an attenuation given by: Z A (db) = 2 log 1 + 2R d Pin Diode Schottky Diode At very low R d, most of the incident power is reflected back to the source, the aerial. As a result, the limiter is able to handle incident RF power, Pi, much higher than its maximum power rating would suggest [2]. Figure 2. (top) A Schottky-assisted PIN limiter consisting of separate PIN and Schottky diodes mounted on a microstrip-type PCB; (middle) Internal configuration of the HSML-2822 combined Schottky-PIN limiter; and (bottom) Typical placement of the HSML-2822 limiter on a CPW-type PCB. 2

3 Limiter Evaluation Board The evaluation limiter was assembled on a PCB consisting of coplanar waveguide with ground plane (CPWG) [6] on a.8 mm thick FR4 dielectric. The CPWG trace is dimensioned for a 5 Ω characteristic impedance and was designed with the aid of the RF design freeware AppCAD [7]. The CPWG trace length from one edge to the opposite edge of the PCB is 25.4 mm (1 ). Input and output connections to the limiter are from edge-launched SMA to PCB transitions (Johnson ) soldered at both ends of the CPWG trace. The HSML-2822 is soldered at the approximate centre of the CPWG length, as mounting it at this position allows the evaluation board to be conveniently modelled as symmetrical halves and this simplifies the simulation. The SMA connector nearest to the PIN diode is chosen as the input so that the PIN diode can protect the more fragile Schottky diode from high incident Pi. Design Simulation The simulation uses a 3-level hierarchy: the complete limiter (top level), evaluation board and packaged device (intermediate level), and diode chips (bottom level). The packaged device s equivalent circuit consists of package parasitics (bond-wire inductances and adjacent pad capacitances), and Schottky Spice [8] and PIN APLAClimited [9] diode models. The Schottky and PIN diode models are implemented using the non-linear PN junction diode [9] and the Symbolically Defined Device (SDD) [1] functions respectively found in the Agilent Technologies ADS26 simulation software. Figure 3. AppCAD screen for CPWG design. Critical dimensions are trace width, W; spacing, G; and dielectric thickness, H. 3

4 DC_Block1 PcbHalf X4 PcbHalf X5 DC_Block2 COAX MID COAX MID 3 Term1 Num=1 Z=5 1 2 hsml5822 X6 Term2 Num=2 Z=5 Figure 4A. Simulation circuit of the complete limiter assembly CPWSub coax Num=1 TL1 A=1.25 mm Ri=4.6 mm Ro=5.3 mm L=9.375 mm T=1.3 um Cond1=4.1E7 Cond2=1.5E Er=2.17 TanD=.1 CPWG CPW1 Subst="CPWSub1" W=45 mil G=15 mil L=.5 in Half of sk63a demonstration board mid Num=2 CPWSub1 H=32 mil Er=4.6 Cond=5.88E7 T=1.4 mil TanD=.2 Var Eqn P1 Num=1 VAR1 Lb=.6 Ll=.1 Cc=35 Cp=3 Rb=.5 Rl=.2 L1 L=Ll nh R=Rl C2 C=Cp ff p382x D1 L2 L=Lb nh R=Rb C1 C=Cc ff P3 Num=3 L5 L=Ll nh R=Rl C3 C=Cp ff DIODE1 Periph= Scale= Trise= L3 L=Lb nh R=Rb L4 L=Ll nh R=Rl P2 Num=2 HSMS282 Is=1.48E-8 Rs=7.8 Gleak= N=1.67 Cd= Cjo=.45 pf Vj=.65 M=.5 Imelt= Bv=26.7 Ibv=1 A Jsw= Rsw= Gleaksw= Ns= Ikp= Cjsw= Msw= Vjsw= Fcsw= AllowScaling=no Trise= Xti=2 Eg=.69 Figure 4B. Simulation circuit of one-half of the evaluation board, including the RF coaxial connector, and packaged device containing the PIN and Schottky diodes 4

5 P1 L L=L Rmin R=Rmin SDDNP1 I [1,]=(_v1)/(A/((1e 26) +_c1)**k) C[1]= Id C C=C DC_Block1 DIODEM1 Is=38 pa Rs= N=1. Tt=7 nsec Cjo= pf Var Eqn global VAR1 Rmin=1.35 Tmax=5k A=.8 K=.9 L=.1 nh C=1.4 pf Rmax R=Rmax DIODE1 Model=DIODEM1 Temp=my Temp DC_Feed1 Id P2 Figure 4C. Simulation circuit of the PIN diode APLAC limited model Results The assembled limiter results shown in Figure 5 demonstrates a useable low insertion loss, A, of under -1 db over more than three frequency decades, 1 MHz to 1.7 GHz, The lower operating frequency range limit is imposed by the capacitance of the DC blocking capacitors in series with the transmission lines. The upper frequency limit is set by the device parasitic capacitances shunting part of the signal to ground. The CPWG transmission lines and coaxial-to-pcb transitions also contribute to the overall A, approximately.2 db at 1.7 GHz. The measured and simulated results for both small signal insertion loss, A, and return loss, RL, versus frequency demonstrates a close agreement in the limiter s useable frequency range of 1~17 MHz. As shown in Figure 6, a significant difference between simulated and measured results occurs only outside the operating range, above 4 GHz. The notch in the A versus. frequency trace around 4.5 GHz is probably caused by the series resonance of the package and diode chips parasitic reactances that create a low impedance path between the CPWG and ground. The Agilent Technologies ADS26 harmonic balance and large signal S-parameters solvers [11] are used to simulate swept power results. P th occurs around 2 dbm at 45 MHz and 5 dbm at 2 GHz. The discrepancy between measured and simulated A versus Pi performance is less than 1 db below P th and less than 3 db above P th, as shown in Figure 7. High incident RF power, Pi, drives both PIN and Schottky diodes to generate distortion products. In the measurement results this is shown by the 2 nd harmonic increasing at a 2 to 1 rate (db) with Pi. However, the APLAC-limited model is a linear one and therefore cannot predict the PIN diode contribution to the overall distortion [9]. Fortunately, the Schottky diode generates higher nonlinearity amplitudes than the PIN diode and so the former dominates the simulated results leading to a useable limiter model. Figures 8 and 9 show fundamental and 2 nd harmonic output power versus input power at 45 MHz and 2 GHz. Both measured and simulated results are shown. 5

6 db A vs Freq before and after compensating for test fixture losses before after board loss (w.o. DUT) -2 Start: Hz Stop: 2. GHz sk63 Pi=-3 dbm Figure 5. Small signal Insertion loss (A) of limiter evaluation board before and after compensating for the test-board losses db RL and A simulated vs measured A mes RL mes A sim RL sim -25 Start: 5. MHz 5m~6g, 41p Stop: 6. GHz Figure 6. Small signal Insertion (A) and Return (RL) losses versus Frequency: Measured and simulated resuls Attenuation vs input power at.45 and 2 GHz 45 MHz mes 45 MHz sim 2 GHz mes 2 GHz sim -2 Start: -2. dbm Pin Stop: 25. dbm Figure 7. Attenuation versus power as a function of frequency (Including test-board and connector losses) dbm Fundamental and 2nd harmonic output vs input power at 45 MHz: measured and simulated Start: -2. dbm Pi fund mes 2H mes fund sim 2H sim Stop: 25. dbm Figure 8. Fundamental and 2nd harmonic output power versus input power (Pi) at 45 MHz: Measured and simulated dbm Measured and simulated output vs input power at 2 GHz fund mes -5 2H mes -6 fund sim -7 2H sim -8 Start: -2. dbm Pi Stop: 25. dbm Figure 9. Fundamental and 2nd harmonic output power versus input power, Pi, at 2 GHz; Measured and simulated 6

7 Conclusion A complete hybrid Schottky-PIN diode limiter has been integrated into a tiny and low cost SOT-323 package. The limiter exhibits low P th, and low A over a wide useable frequency range. A model has also been created that gives reasonably accurate simulation results for both linear and nonlinear limiter characteristics. References 1. Avago Technologies data sheet, ATF Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package, [Online] Available: avagotech.com 2. Avago Technologies application note 15, Low Cost Surface Mount Power Limiters, [Online] Available: 3. Avago Technologies product specification, Surface Mount RF PIN Switch and Limiter Diodes: HSMP-382x Series and HSMP-482x Series, [Online] Available: 4. C. Straelhi et al, P-i-n and varactor diodes in The Microwave Engineering Handbook, vol. 1, B. L. Smith and M. H. Carpentier, Eds. London: Chapman & Hall, 1993, pp Skyworks product specification, Limiter Diodes, [Online] Available: 6. W. R. Deal, Coplanar Waveguide Basics for MMIC and PCB Design, IEEE Microwave Magazine, pp , Aug AppCAD for Windows v.3..2, Available: avagotech.com/docs/ Avago Technologies application note 1187, Design of an Input Matching Network for a DC biased 85 MHz Small signal Detector, [Online] Available: avagotech.com 9. HPRFhelp PIN diode SPICE library, PIN Diode Models for HSMP-382x series [Online] Available: hp.woodshot.com/hprfhelp/design/spice/pins. htm#hsmp382x 1. Agilent Technologies EESOF Knowledge Center ADS support example, How to create a model for the junction resistance of the PIN diode?, [Online] Available: Agilent Technologies EESOF product specification, Guide to Harmonic Balance simulation in ADS, [Online] Available: com For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV2-2139EN - August 19, 21