CGY2107HV CGY2107HV PRODUCT DATASHEET. Dual High Gain Low Noise High IP3 Amplifier. Rev 0.2 FEATURES APPLICATIONS DESCRIPTION

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1 Rev 0.1 PRODUCT DATASHEET Dual High Gain Low Noise High IP3 Amplifier DESCRIPTION The is an extremely Low Noise cascode Amplifier with state of the art Noise Figure and Linearity suitable for applications from 500 MHz to MHz. The consists of two identical amplifiers on the same MMIC, and is ideal for use in a balanced configuration or as two single ended amplifiers. Used as a balanced amplifier with 3 db couplers, a 0.63 db Noise Figure, 34 dbm Output IP3 and 23.5 db Gain is obtained at 1.9 GHz. At 3.5 GHz a balanced demonstrator exhibits 0.85 db Noise Figure, 19.5 db Gain and OIP3 of 37 dbm. These are measured values and include the noise contribution of the couplers, connectors and biasing circuitry. The minimum Noise Figure of the itself is 0.32 db at 1.9 GHz. The MMIC is manufactured using s qualified 0.25 µm PHEMT GaAs MMIC technology. The device is available in a 4x4 mm QFN plastic package. APPLICATIONS High performance LNA in the band GHz Base Station applications (LTE, GSM, CDMA, WCDMA, TD-SCDMA, CDMA2000, WiMAX, etc) Tower mounted amplifiers Repeaters FEATURES RF IN Usable frequency range from 500 MHz to 6000 MHz Dual MMIC LNA with excellent tracking Amplifier NFmin@1.9GHz = 0.32 db Low Noise, High Gain and high IP3 in balanced configuration : NF=0.63 db, Gain=23.5 db, OIP3= GHz NF=0.7 db, Gain=21 db, OIP3= GHz NF=0.85 db, Gain=19.5 db, OIP3= GHz Uses a highly reliable PHEMT MMIC process Delivered as 100 % RF tested devices Samples and Demonstration Boards Available Space and MIL-STD Available 3dB coupler Biasing&matching circuitry Biasing&matching circuitry V EE1 V EE2 V DD1 V DD2 Biasing&matching circuitry Biasing&matching circuitry Schematic diagram of the used in a balanced configuration. 3dB coupler RF OUT The is RoHS compliant.

2 LIMITING VALUES T amb = + 23 C, at QFN package lead; unless otherwise specified. Symbol Parameter Conditions MIN. MAX. UNIT V EE1, V EE2 Gate voltage V DD open-circuited V V DD1, V DD2 Drain voltage V EE open-circuited V I D1, I D2 Drain current 100 ma P IN Input power 10 dbm T amb Ambient temperature C T j Junction temperature +150 C T stg Storage temperature C THERMAL CHARACTERISTICS Symbol Parameter Value UNIT R th (j-a) Thermal resistance from junction to ambient (T a = 25 C) 70 C/W CHARACTERISTICS T amb = + 23 C Symbol Parameter Conditions MIN. TYP. MAX. UNIT f i Input frequency GHz Performance at QFN package lead; f i = 1.9 GHz V D Supply voltage 4 V I D Supply current V EE = V 50 ma G Gain 22.7 db NF min Minimum Noise Figure 0.32 db Performance * of Reference Board (Single Ended configuration with on-board bias resistors); f i = 1.95 GHz V DD Supply voltage 5 V I D Supply current V EE1 = V EE2 = V 50 ma G Gain db NF Noise Figure 0.5 db ISO rev Reverse Isolation OUT/IN 32 db IIP3 Input third order intercept point I D = 70 ma dbm S 11 Input reflection coefficient 50 Ω source db S 22 Output reflection coefficient 50 Ω load - 10 db ISO IN1-IN2 Isolation between IN1 and IN2 IN1/IN2 30 db Performance * of Demonstration Board (Balanced configuration with on-board bias resistors); f i = 1.9 GHz V DD1, V DD2 Supply voltage 5 V I D1, I D2 Supply current V EE1 = V EE2 = V 50 ma G Gain 23.4 db NF Noise Figure 0.63 db IIP3 Input third order intercept point 11 dbm P 1dB Output 1dB gain compression 22 dbm S 11 Input reflection coefficient 50 Ω source db S 22 Output reflection coefficient 50 Ω load db (*) Measurement reference planes are the INPUT and OUTPUT SMA connectors. Caution : This device is a high performance RF component and can be damaged by inappropriate handling. Standard ESD precautions should be followed. document OM-CI-MV/ 001/ PG contains more information on the precautions to take. 2 / 10

3 S-PARAMETERS V D = 4 V; I D = 50 ma; T amb = + 23 C Frequency (GHz) S11 Ang S11 ( ) S21 Ang S21 ( ) S12 Ang S12 ( ) S22 Ang S22 ( ) Note : Measurement reference planes are the QFN Package Leads, a TRL calibration method is used. 3 / 10

4 NOISE-PARAMETERS V D = 4 V; I D = 50 ma; T amb = + 23 C. Frequency (GHz) NF min (db) Γ opt Ang Γ opt ( ) R n Note : The reference planes are the QFN Package Leads. R n0 is the Noise Resistance normalised to 50 Ω. 4 / 10

5 SINGLE ENDED REFERENCE BOARD 1900 MHZ Assembly Drawing. Circuit Diagram (centre frequency 1900 MHz). VEE2 VEE1 - VEE2 - VEE1 C10 C3 IN2 IN2 R3 C9 C11 C4 C2 R1 IN1 IN1 TRL3 TRL1 C8 L3 L1 C1 TRL4 TRL2 C13 L4 L2 C6 C14 R4 R2 C7 C12 C5 VD2 + VD2 T15R29 R1 + VD1 VD1 OUT2 OUT1 OUT2 OUT1 Bill of materials Printed Circuit Board Component Value Reference R1, R3 470 Ω 0603 R2, R4 22 Ω 0603 L1, L3 22 nh Coilcraft 0805CS L2, L4 22 nh Toko 0603 C1,C8 47 pf 0603 C0G C2,C9 10 pf 0603 C0G C3,C10 15 pf 0603 C0G C4,C11,C7,C14 10 nf 0805 C5, C12,C6,C pf 0603 C0G C15,C16 47 µf 1210 X5R TRL1, TRL3 W=150 µm l=3000 µm TRL2, TRL4 W=150 µm l= µm Notes: Capacitors C17 and C18 prevent low frequency oscillations when the board is biased from laboratory power supplies. They are not required when on-board voltage regulators are used. Board material is Rogers RO4350 with height 508 µm. 5 / 10

6 MEASURED PERFORMANCE OF REFERENCE BOARD 1900 MHZ Conditions : V DD1 = V DD2 = 5 V, I D1 + I D2 = 100 ma;t amb = + 23 C, unless otherwise stated. Measurements include RF connector contributions. Product Datasheet 0 Input Reflection (S11) 30 Transmission (S21) S11 (db) S21 (db) Frequency (GHz) Frequency (GHz) S22 (db) Output Reflection (S22) Frequency (GHz) S12 (db) Isolation (S12) Frequency (GHz) K factor Stability factor k Frequency (GHz) 6 / 10

7 Insertion Gain (db) Product Datasheet NF versus Frequency NF versus I D current at 1900MHz 0,6 0,55 0,5 25, ,5 NF (db) 0,45 0,4 V DD = 4 V V DD = 5 V 24 23,5 0, ,3 22, I D (ma) Gain versus Temperature NF versus Temperature Note : These results have been obtained on a Single Ended Reference Board optimised at 1950 MHz. Excellent results have been reached in balanced configuration. The frequency range of the Balanced Configuration is mainly determined by the couplers used - the can be used up to 6 GHz, in balanced or single ended applications, with excellent results. For more details on the reference board used, please refer to application notes. 7 / 10

8 BLOCK DIAGRAM AND PIN CONFIGURATION IN OUT1 GND GND OUT2 CGY IN2 IN CGY IN Block Diagram of the LNA. Bottom view OUT1 GND GND OUT2 Pin Diagram of the LNA. PINNING Symbol Pin Description 1, 2, 4, 5 and 6 Amplifier 1 : Source IN1 3 Amplifier 1 : Gate (RF input) OUT1 16 Amplifier 1 : Drain (RF output) 7, 8, 9, 11 and 12 Amplifier 1 : Source IN2 10 Amplifier 2 : Gate (RF input) OUT2 13 Amplifier 2 : Drain (RF output) GND 14 and 15 Ground Note : It is essential in order to ensure good performance and stability that the central ground pad of the QFN package is suitably connected to the ground. 8 / 10

9 PACKAGE Type Description Terminals Pitch (mm) Package size (mm) QFN Quad Flat No lead with exposed heat sink x 4 x 0.9 In agreement with JEDEC MO-220. PACKAGE OUTLINE AND PCB LAND PATTERN A3 Term inal 1 Index area L E E2 b e Detailed view D A A1 D2 DIMENSIONS (mm) D E A A1 A3 Min Nom Max DIMENSIONS (mm) D2 E2 b e L Nom This package is in agreement with JEDEC MO-220 Top view Bottom view ORDERING INFORMATION Generic type Package type Version Sort Type Description CGY2107 HV C1 DUAL LNA, QFN Plastic Package CGY2107 HV C1 REFBOARD Single Ended Reference Board 1900MHz CGY2107 HV C1 BALBOARD Balanced Reference Board 1900MHz THE IS ROHS COMPLIANT. 9 / 10

10 DEFINITIONS Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. s customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify for any damages resulting from such application. Right to make changes reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 03/10/ / 10