PRELIMINARY DATASHEET

Transcription

1 PRELIMINARY DATASHEET GHz 39dBm Ka Power Amplifier DESCRIPTION The is a high performance GaN Power Amplifier MMIC designed to operate in the Ka band. The has an output power of 8 W at the 1dB compression point and a small signal gain of 22 db. These performances make it well suited to be used in Radar, Telecommunication and Satcom applications. The die is manufactured using s High Performance 0.1 µm gate length GaN on Si PHEMT Power Technology. The MMIC uses gold bonding pads and backside metallization and is fully protected with Silicon Nitride passivation to obtain the highest level of reliability. Thanks to the GaN on Si advanced power process, 12V Drain voltage can be used. FEATURES Operating Range : 28 GHz to 31.5 GHz Output P sat : GHz Gain : 22 db 50 Ohms input and output matched Power Supply : VD=12V IDQ = 0.7 A Chip size = 4.54 x 3.51 mm 50 Ohms input and output matched Device Availability (Q1 2017) : Tested, Inspected Known Good Die (KGD) Demonstration Boards Space and MIL-STD MMICs VD1N VD2N VD3N APPLICATIONS Radar RFIN VG1N VG1S VG2N VG2S VG3N VG3S RFOUT Telecommunications VD1S VD2S VD3S Satcom Power Amplifier Block Diagram Revision : 08/12/ information@ommic.com

2 MAXIMUM VALUES 2 / 14 Symbol Parameter Conditions MIN. MAX. UNIT VG1N, VG2N, VG3N, VG1S, VG2S, VG3S VD1N, VD2N, VD3N, VD1S, VD2S, VD3S Gate voltage - 2,5 0 V Drain voltage V IDQ1N, IDQ1S 200 IDQ2N, IDQ2S Drain current 400 ma IDQ3N, IDQ3S 600 IGNN, S (all gates) Gate Current ma PIN RF Input power + 23 dbm Tamb Ambient temperature C Tj Junction temperature C Tstg Storage temperature C Operation of this device outside the parameter ranges given above may cause permanent damage THERMAL CHARACTERISTICS Symbol Parameter Value UNIT Rth (j - amb) Thermal resistance from junction to ambient (DC power at Tamb max) TBD C/W ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions MIN. TYP. MAX. UNIT RFin Input frequency GHz VD1N, 2N, 3N VD1S, 2S, 3S Drain Supply voltage 12 V IDD Total supply Psat Drain voltage 12V 2.5 A G Gain 22 db Psat Saturated power 39.0 dbm PAE Power Added Efficiency PAE at 30 Ghz 26 % OIP3 Output third order intercept point TBD dbm IMD3 2 Carriers 3 db below P1dB TBD dbc S11 Input reflection coefficient 50 Ohms -10 db S22 Output reflection coefficient 50 Ohms -9 db POFF Leakage when HPA off All gates = -2,5V RFIN = + 20 dbm TBD dbm (*) Measurement reference planes are the INPUT and OUTPUT plans of the MMIC. Caution : This device is a high performance RF component and can be damaged by inappropriate handling. Standard ESD precautions should be followed. document OM- CI-MV/ 001/ PG contains more information on the precautions to take.

3 Conditions: On wafer measurements with a pulse test bench to assure a full polarization conditions and cold channel temperature. This method also remove the risk of reliability damages due to high temperature overstress inherent to on wafer measurements at full polarization and reflects the performances of the devices in good cooling conditions. VD3N, VD3S = VD2N, VD2S = VD1N, VD1S = 12V ; I DQ3N, I DQ3S = 400mA, I DQ2N, I DQ2S = 200mA, I DQ1N, I DQ1S = 100mA ; duty cycle 1%, Tamb = + 25 C Typical performance-small signal 3 / 14

4 4 / 14 Typical performance-small signal

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6 6 / 14 APPLICATION SCHEMATIC Decoupling scheme depends on customer implementation, in order to prevent unstability it is hightly recommended to place a 47pF RF decoupling chip capacitor at each DC terminal with the shortest possible bonding wires. Additionnaly, a 10nF chip capacitor can be added on the drain 3 connection. The decoupling network depends on supply, on grounding environment, on form factor, on all parasitics added by customer environment. According to this, the appropriate network sometimes need to be fine-tuned in accordance with rules applyable in the millimeter wave frequency domain. It may also be required to add very low frequency, high capacitor value. On each drain a 10 Ohms / 10 nf RC serie network made of 0402 format capacitors have been implemented reference test-jig.

7 7 / 14 VD_1N VG_1N VD_2N VG_2N VD_3N VG_3N 47pF* 10 nf* 47pF* 10 nf* 47pF* 10nF* 220 nf 220 nf 220 nf 47pF* 47 1 uf 47pF* 22 1 uf 47pF* 1 uf VD1N VG1N VD2N VG2N VD3N VG3N MMIC Contain RFIN RFOUT VD1S VG1S VD2S VG2S VD3S VG3S 47pF* 47 1 uf 47pF* 22 1 uf 47pF* 1 uf 47pF* 10 nf* 47pF* 10 nf* 47pF* 10 nf* 220 nf 220 nf 220 nf VD_1S VG_1S VD_2S VG_2S VD_3S VG_3S Figure 1: Application Schematic Notes: components identified with a (*) are chip capacitors bounded as closed as possible to the chip.

8 Component NAME Value Type Comment Preliminary Datasheet All 47pF capacitors 47pF Chip Capacitor Chip capacitor PRESIDIO COMPONENTS P/N SA151BX470M2HX5#013B soldered close to the die with bonding as short as possible All 10nF capacitors 10nF Chip Capacitor MURATA GMA085R71C103MD01T GM260 X7R 103M 16M100 PM520 8 / 14 Due to the highly symmetrical design of the component and the requirements of the power combiner, it is recommended to keep the supply design as symmetrical as possible, this means IDQ1N equal to IDQ1S, IDQ2N equal to IDQ2S and IDQ3N equal to IDQ3S, for the same reason, it is recommended to keep VD1N equal the VD1S, VD2N equal the VD2S and VD3N equal the VD3S. It is important to keep VG1N equal the VG1S, VG2N equal the VG2S and VG3N equal the VG3S. can be supplied with only a single pulsed Vd voltage and only a single Vg voltage. Nevertheless, it is very important to keep efficient decoupling networks on drain and gates. Improper decoupling networks can lead to oscillations through supply guided feedback loop. have been designed to present a 50 Ohms plan at the die port. 2 to 3 standard wire bondings (25um in diameter 300um in length) can be used to connect the die to the environment (microstrip or coplanar). The wire bonding terminal (alumina or PCB substrate) should be build to compensate the inductance introduced by the wire bounding over the frequency band. As the use of different Vg on each stage can be used to optimize a particular parameter corresponding to customer demand, all Vg are left available to the customer. Customised board available

9 PAD LAYOUT 9 / 14 The Die is symetrical on the RF axis. The die positionned top view with RF input on the left and RF output on the right show DC accesses on the top labelled north (N) and DC accesses on the bottom labelled south (S). VD1A, VD2A, VD3A, VG1A, VG2A, VG3A are DC signals applied on the north side while VD1B, VD2B, VD3B, VG1B, VG2B, VG3D are DC signals applied on the south side. Many ground accesses are complementing the pad layout. The backside is the ground reference plan. Additionnal pads have been added and are used during testing, this dedicated pads are called SENS3A,SENS2A,SENS3B,SENS2B and are used to sense drain voltages as near as possible to the chip. Figure 2: Pad allocation PAD COORDINATES The Die is symetrical on the RF axis. The die positionned top view with RF input on the left and RF output on the right show DC accesses on the top labelled north (pads identified with A termination on the die) and DC accesses on the bottom labelled south (pads identified with B termination on the die).

10 10 / 14 PINOUT Figure 3: pad coordinates The amplifier has a North face and a south face, north is top and south is bottom when RF input is on the left an RF output on the right. Symbol Pad Description RFOUT OUT RF output RFIN IN RF input VD1N VD1A First stage Drain (amplifier North) VD2N VD2A Second stage Drain (amplifier North) VD3N VD3A Third stage Drain (amplifier North) VG1N VG1A First stage Gate (amplifier North) VG2N VG2A Second stage Gate (amplifier North)

11 VG3N VG3A Third stage Gate (amplifier North) SENS2N SENS2A Second stage Drain Sense (amplifier North) SENS3N SENS3A Third stage Drain Sense (amplifier North) VD1B VD1B First stage Drain (amplifier South) VD2B VD2B Second stage Drain (amplifier South) VD3B VD3B Third stage Drain (amplifier South) VG1B VG1B First stage Gate (amplifier South) VG2B VG2B Second stage Gate (amplifier South) VG3B VG3B Third stage Gate (amplifier South) SENS2S SENS2B Second stage Drain Sense (amplifier South) SENS3S SENS3B Third stage Drain Sense (amplifier South) GND BACKSIDE Ground 11 / 14 Note : In order to ensure good RF performances and stability It is key to connect to the ground the pad available on the backside of the die. BONDINGS PAD COORDINATES Symbol X coordinate (um) Y coordinate (um) Pad size (um x um) GND , x 97 (associated with RFOUT pad) RFOUT x 277 GND x 97 (associated with RFOUT pad) GND x 97 (associated with RFIN pad) RFIN x 247 GND x 97 (associated with RFIN pad) GND x 107 VG1N x 107 GND x 107 VG2N x 107 GND x 107 VG3N x 107 GND x 107 VD1N x 107 VD2N x 107 SENS2N x 107 GND x 107 GND x 107

12 SENS3N x 107 VD3N x 107 GND x 107 VG1N x 107 GND x 107 VG2N x 107 GND x 107 VG3N x 107 GND x 107 VD1N x 107 VD2N x 107 SENS2N x 107 GND x 107 GND x 107 SENS3N x 107 VD3N x 107 GND BACKSIDE Ground 12 / 14 PACKAGE Figure 4: OMM2650UH/C1 Pad Corrdinates Type Description Terminals Pitch (mm) Package size (mm) DIE 100% RF and DC on-wafer tested x 3.51 x 0.1 SOLDERING To avoid permanent damages or impact on reliability during soldering process, die temperature should never exceed 330 C. Temperature in excess of 300 C should not be applied to the die longer than 1mn Toxic fumes will be generated at temperatures higher than 400 C

13 13 / 14 ORDERING INFORMATION Generic type Package type Version Sort Type Description CGY2650 UH C1 - On-Wafer measured Die CGY2650 UH C1 EK Test-jig

14 DEFINITIONS 14 / 14 Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. s customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify for any damages resulting from such application. Right to make changes reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.