PRELIMINARY DATASHEET

Transcription

1 PRELIMINARY DATASHEET Ultra Low Noise GHz Amplifier DESCRIPTION The CGY2121XUH is a high performance GaAs Low Noise Amplifier MMIC designed to operate in the K band. The CGY2121XUH has an exceptionally low noise figure of 1.2 db with 17 db of gain at 22 GHz. The on chip matching provides 13 db of Input Return Loss and 20 db of Output Return Loss at 22 GHz. It can be used in Radar, Telecommunication and Instrumentation applications. The die is manufactured using s Advanced 70 nm gate length high Indium content MHEMT Technology. The MMIC uses gold bonding pads and backside metallization and is fully protected with Silicon Nitride passivation to obtain the highest level of reliability. FEATURES Operating frequency range : 18 to 26 GHz Noise Figure : 1.2 db at 22GHz 50 Ohms input and output matched Input Return Loss : > 12 db at 22GHz Output Return Loss : > 19 db at 22GHz Die size = 1.5 x 2.0 mm Device Availability (Q4 2011) Tested, Inspected Known Good Die (KGD) Demonstration Boards Vd1 Vd2 APPLICATIONS Radar Telecommunications Instrumentation RFin 1st Stage Vg1 2nd Stage Vg2 CGY2121XUH block diagram RFout Revision : 19/10/ information@ommic.com

2 MAXIMUM VALUES T amb = + 25 C, at QFN package leads; unless otherwise specified. Preliminary Datasheet Symbol Parameter Conditions MIN. MAX. UNIT Vg1, Vg2 Gate voltage VDD Open circuit V Vd1, Vd2 Drain voltage VDD Open circuit V Id1, Id2 Drain current 200 ma P IN RF Input power + 10 dbm Tamb Ambient temperature C Tj Junction temperature C Tstg Storage temperature C Operation of this device outside the parameter ranges given above may cause permanent damage 2 / 12 THERMAL CHARACTERISTICS Symbol Parameter Value UNIT Rth (j - amb) Thermal resistance from junction to ambient (DC power at Tamb max) TBD C/W ELECTRICAL CHARACTERISTICS T amb = + 25 C, V d1, V d2 = 0.8V, I d1 + I d2 = 60mA Symbol Parameter Conditions MIN. TYP. MAX. UNIT RFin Input frequency GHz Performances on Reference Board at f i = 22 GHz V DD1, V DD2 Drain Supply voltage V I D1, I D2 Drain Supply current 60 ma G Gain 17.5 db NF MIN Noise Figure 1.2 db P1dB 1dB compression point TBD dbm Psat Saturated power TBD dbm OIP3 Output third order intercept point TBD dbm IMD3 2 Carriers 3 db below P1dB TBD dbc ISO rev Reverse Isolation RFOUT/RFIN -29 db S 11 Input reflection coefficient 50 Ohms -12 db S 22 Output reflection coefficient 50 Ohms -19 db P OFF Leakage when LNA off Vg1,g2 = -2,5V RFIN = + 17 dbm TBD dbm (*) Measurement reference planes are the INPUT and OUTPUT plans of the CGY2121XUH MMIC. Caution : This device is a high performance RF component and can be damaged by inappropriate handling. Standard ESD precautions should be followed. document OM- CI-MV/ 001/ PG contains more information on the precautions to take.

3 CGY2121XUH have been measured on-wafer this method assure a full polarization conditions 3 / 12 S-PARAMETERS (SMITH CHARTS) Conditions : Vd1, d2 = 0.8V, Id1 + Id2 = 60mA, Tamb = + 25 C (On carrier measurements) Figure 1 : S11 measurements Figure 2 : S22 measurements

4 4 / 12 Figure 3 : Gain and reverse isolation S PARAMETERS Conditions : Vd1, Vd2 = 0.8V, Id1+ Id2 = 60mA, Tamb = + 25 C (On-Wafer measurements) GHz S11 S11 Phase S21 S21 Phase S12 S12 Phase S22 S22 Phase

5 NOISE FIGURE Conditions : Vd1, Vd2 = 0.8V, Id1+ Id2 = 60mA, Tamb = + 25 C (On-Wafer measurements) 5 / 12

6 APPLICATION SCHEMATIC 6 / 12 To prevent unstability of the customer design it is hightly recommended to place small chip capacitors as near as possible to the CGY2121XUH die and to connect them with bondings as short as possible. Additionnaly, a 10nF capacitor can be added on a drain connection. In the gate circuitry, a 500 Ω resistor may be added in serie to improve gate isolation and prevent unwanted oscillations. The resistors are introducing some low pass filtering in case of fast power switching using gate control architecture. Depending on 50Ohms connected lines and associated tapers, many connections schemes can be sudied/used regarding Rfin and RF out connections. VD1 VG1 VD2 VG2 47pF 10 nf 47pF 10 nf 47pF 500 Ω 10 nf 47pF 500 Ω 10 nf Vd1 Vg1 Vd2 Vg2 RFIN RFOUT MMIC Contain Figure 4 : Application schematics Component NAME Value Type Comment All 47pF capacitors 47pF Chip Capacitor Chip capacitor PRESIDIO COMPONENTS P/N SA151BX470M2HX5#013B soldered close to the die with bonding as short as possible All 500 Ω resistors 500 Ω Chip Resistor Chip resistor US MICROWAVES RG % soldered close to the 47pF chip capacitor with bonding as short as possible All 10nF capacitors 10nF Chip Capacitor MURATA GMA085R71C103MD01T GM260 X7R 103M 16M100 PM520 Tableau 1 Components reference

7 7 / 12 RFout Vd2 Vg2 Vd1 Vg1 RFin Figure 5 Reference board

8 DIE LAYOUT AND PIN CONFIGURATION 8 / 12 NC Vd1 NC Vd2 RFIN RFOUT Y 0 X NC Vg1 Vg2 NC Figure 6 Pad layout PINOUT The amplifier has a North and South face, North is top and South is Bottom when RF input is on the left and RF output on the right. Symbol Pad Description RFOUT OUT RF output RFIN IN RF input Vd1 VD1 First stage Drain Vd2 VD2 Second stage Drain

9 Vg1 VG1 First stage Gate Vg2 VG2 Second stage Gate GND BACKSIDE Ground 9 / 12 Note : In order to ensure good RF performances and stability It is key to connected to the ground the pad available on the backside of the die. BONDINGS PAD COORDINATES MMIC Steps on the wafer are 1.5 and 2 mm along X and Y coordinated respectively, dicing typically reduce the die size by 80um. Dicing introduce uncertaincy on overall device size All coordinates refered to point 0 wich is le bottom left point of the device at the border of the sawing aera Sawing Channel Point Coordinate 0,0 Figure 7 Pad coordinate reference (Not CGY2121XUH die) Die reference positioning The amplifier has a North and South face, North is top and South is Bottom when RF input is on the left and RF output on the right. DC pads On North side of the CGY2121x die, 5 pads 80 x 80 ums steps 300um offset 125um from point 0 can be found On South side of the CGY2121x die, 5 pads 80 x 80 ums steps 300um offset 75um from point 0 can be found

10 10 / 12 RF pads RF pad support coaxial / microstrip architecture, RF pad size is 80 x 80 um and GND pads are 60 x 100 um Spacing between RF and GND pads are 150um X and Y coordinates refer to the center of the different pads Symbol Pad X coordinate Pad Y coordinate Pad size RFOUT RF 80 x 80 - GND 60 x 100 Spacing 150um RFIN RF 80 x 80 - GND 60 x 100 Spacing 150um Vd um x 80 um GND(North) um x 80 um Vd um x 80 um Vg um x 80 um GND(South) um x 80 um Vg um x 80 um GND BACKSIDE BACKSIDE Ground Figure 8 : pad coordinates PACKAGE Type Description Terminals Pitch (mm) Package size (mm) DIE 100% RF and DC on-wafer tested x 2 x 0.1 ORDERING INFORMATION Generic type Package type Version Sort Type Description CGY212X UH C1 - On-Wafer measured Die

11 SOLDERING Preliminary Datasheet To avoid permanent damages or impact on reliability during soldering process, die temperature should never exceed 330 C. Temperature in excess of 300 C should not be applie d to the die longer than 1mn Toxic fumes will be generated at temperatures higher than 400 C 11 / 12

12 DEFINITIONS 12 / 12 Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. s customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify for any damages resulting from such application. Right to make changes reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.