QPL9096 Ultra Low-Noise, Bypass LNA

Transcription

1 General Description The is a high-linearity, ultra-low noise gain block amplifier with a bypass mode functionality integrated in the product. At. GHz, the amplifier typically provides db gain, +. dbm OIP, and. db noise figure while drawing ma current from a +. V supply. The is internally matched using a high performance E-pHEMT process and only requires four external components for operation from a single positive supply: an external choke and blocking/bypass capacitors. This low noise amplifier contains an internal active bias to maintain high performance over temperature. The is optimized for the.. GHz frequency band and is targeted for wireless infrastructure. The is packaged in a x mm DFN. Product Features Pin X mm DFN Package.. GHz Operational bandwidth LNA with integrated bypass mode Ability to turn LNA and bypass mode OFF Ultra low noise,. db at. GHz db Gain at. GHz +. dbm Output IP in + dbm Input IP in Internally matched Positive supply only, +. to + V x mm -pin DFN plastic package Functional Block Diagram Applications GND In N/C Pin Reference Mark V DD Out GND Base-station Receivers Repeaters / DAS Tower Mounted Amplifiers Mobile Infrastructure General Purpose Wireless TDD or FDD systems V BYP V SD Backside Paddle - /DC GND Top View Ordering Information Part No. Description SR pcs on reel TR pcs on reel EVB () Evaluation Board. Refer board details and performance on pgs. &. Data Sheet July, Subject to change without notice of

2 Absolute Maximum Ratings Parameter Rating Storage Temperature to C Supply Voltage (VDD) Input Power, CW, Ω, T= C + V + dbm Operation of this device outside the parameter ranges given above may cause permanent damage. Recommended Operating Conditions Parameter Min Typ Max Units Supply Voltage (VDD)... V TCASE + C Tj at TCASE = C + C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: VDD = +. V, Temp.=+ C. Parameter Conditions Min Typ Max Units Operational Frequency Range MHz Test Frequency MHz Gain LNA ON, Bypass OFF.. db Input Return Loss LNA ON, Bypass OFF db Output Return Loss LNA ON, Bypass OFF db Noise Figure () LNA ON, Bypass OFF.. db Output PdB LNA ON, Bypass OFF +. () + dbm Output IP LNA ON, Bypass OFF, Pout=+ dbm/tone, Δf= MHz + +. dbm Insertion Loss LNA OFF, Bypass ON. db Return Loss LNA OFF, Bypass ON db Isolation () LNA OFF, Bypass OFF db Output IP LNA OFF, Bypass ON Pin=+ dbm/tone, Δf= MHz + + dbm Control Voltage, V, V VIH. VDD V VIL. V Current, ID Switching Speed Bypass OFF ma Bypass ON. ma LNA-Bypass (% Vctrl to % ) ns Bypass-LNA(% Vctrl to 9% ) ns LNA-OFF(% Vctrl to % ) ns OFF-LNA(% Vctrl to 9% ) ns Thermal Resistance, θjc Channel to case C/W. Minimum specification listed is guaranteed by design. Not tested in production.. Input trace loss de-embedded from noise figure data. Control Truth Table VBYP VSD State LNA ON, Bypass OFF LNA OFF, Bypass OFF x LNA OFF, Bypass ON Data Sheet July, Subject to change without notice of

3 Evaluation Board C R J V DD J GND R pf C C R C U L C R C U L nh () uf J Input C pf C pf J Output C C K K C C R R. A through line is included on the evaluation board to de-embed the board losses. J V J V Bill of Material Evaluation Board Reference Des. Value Description Manuf. Part Number N/A N/A Printed Circuit Board Qorvo U n/a Ultra Low Noise, Bypass LNA Qorvo C, C, C, C pf CAP,, +/-.pf, V Various pf CAP,, %, V, XR Murata GRMRHKAD C. uf Cap.,, %,.V, XR Murata GRMRJKE9D C, C K RES, chip,, % Various R,, Ω Resistor, Chip,, %, /W various L nh Inductor,, %, coil Coilcraft CS-NXJL Data Sheet July, Subject to change without notice of

4 OIP (dbm) OIP (dbm) Noise Figure (db) Gain (db) S (db) S (db) Insertion Loss (db) S (db) S (db) Gain (db) S (db) S (db) Performance Plots Test conditions unless otherwise noted: VDD = +. V Gain vs. Frequency () +9 C + C C - Input Return Loss vs. Frequency () - Output Return Loss vs. Frequency () +9 C + C C - +9 C + C C Insertion Loss vs. Frequency () Input Return Loss vs. Frequency () Output Return Loss vs. Frequency () C + C C C C + C - + C C -. - C Isolation vs. Frequency (OFF Mode) Input Return Loss vs. Frequency (OFF Mode) Output Return Loss vs. Frequency (OFF Mode) - +9 C + C C C + C - C + C +9 C - C OIP vs Pout/tone () OIP vs Pout/tone (). Noise Figure vs Frequency... + C + C. C.. MHz_-C MHz_-C MHz_-C MHz_C MHz_C MHz_C MHz_9C MHz_9C MHz_9C MHz_-C MHz_-C MHz_-C MHz_C MHz_C MHz_C MHz_9C MHz_9C MHz_9C Frequency (GHz) Data Sheet July, Subject to change without notice of

5 OIP (dbm) OIP (dbm) Gain (db) S & S (db) Noise Figure (db) -9 MHz Tune C R J V DD J GND R pf C C C R L L U C C C R L C U L nh () uf J Input C pf C. pf L.nH C pf L.9nH C pf J Output C C K K C C R R. A through line is included on the evaluation board to de-embed the board losses. J V J V Performance Plots--9 MHz Tune Test conditions unless otherwise noted: VDD = +. V, Temp.= + C Gain vs. Frequency Return Loss vs. Frequency Input Return Loss-. Noise Figure vs Frequency - Input Return Loss- Output Return Loss- Output Return Loss OIP vs Pout/tone OIP vs Pout/tone MHz MHz MHz MHz 9 MHz 9 MHz Data Sheet July, Subject to change without notice of

6 OIP (dbm) OIP (dbm) Gain (db) S & S (db) Noise Figure (db) 9- MHz Tune C R J V DD J GND R pf C C C R L L U C C C R L C U L nh () uf J Input C pf C. pf L.nH C pf L.nH C pf J Output C C K K C C R R. A through line is included on the evaluation board to de-embed the board losses. J V J V Performance Plots-9- MHz Tune Test conditions unless otherwise noted: VDD = +. V, Temp.= + C Gain vs. Frequency Return Loss vs. Frequency. Noise Figure vs Frequency Input Return Loss- Input Return Loss- Output Return Loss- Output Return Loss OIP vs Pout/tone OIP vs Pout/tone MHz MHz MHz MHz 9 MHz 9 MHz Data Sheet July, Subject to change without notice of

7 OIP (dbm) OIP (dbm) Gain (db) S & S (db) Noise Figure (db) - MHz Tune C R J V DD J GND R pf C C R C L U C C C R L C U L nh () uf J Input C pf C. pf C L. pf. nh J Output C C K K C C R R. A through line is included on the evaluation board to de-embed the board losses. J V J V Performance Plots - MHz Tune Test conditions unless otherwise noted: VDD = +. V, Temp.= + C Gain vs. Frequency - Return Loss vs. Frequency Input Return Loss- Input Return Loss- Output Return Loss- Output Return Loss-.. Noise Figure vs Frequency OIP vs Pout/tome OIP vs Pout/tome MHz MHz MHz MHz MHz MHz Data Sheet July, Subject to change without notice of

8 Pin Configuration and Description Pin Reference Mark GND V DD In Out N/C GND V BYP V SD Pin No. Label Description, GND /DC Ground pin. Backside Paddle - /DC GND in input pin. DC block required. N/C No internal connection. Provide grounded PCB land pads for mounting integrity. VBYP Control pin for bypass mode. The LNA is automatically turned off when the bypass mode is activated. Refer to truth table on pg. VSD Control pin to disable the LNA. Refer to truth table on pg.. out output pin. DC block required. VDD Supply voltage pin. External choke and bypass capacitors needed. Backside /DC Ground. Follow recommended via pattern and ensure good solder attach for /DC GND Paddle best thermal and electrical performance. Evaluation Board PCB Information Qorvo PCB Material and Stack-up."." ±." Finished Board Thickness." Rogers C ε r =. typ. FR FR oz. Cu top layer oz. Cu inner layer oz. Cu inner layer oz. Cu bottom layer ohm line dimensions: width =., spacing =. Data Sheet July, Subject to change without notice of

9 Mechanical Information Package Marking and Dimensions 99 Trace Code. All dimensions are in millimeters. Angles are in degrees.. Except where noted, this part outline conforms to JEDEC standard MO-, Issue E (Variation VGGC) for thermally enhanced plastic very thin fine pitch quad flat no lead package (QFN).. Dimension and tolerance formats conform to ASME Y.M-99.. The terminal # identifier and terminal numbering conform to JESD 9- SPP-. PCB Mounting Pattern. All dimensions are in millimeters. Angles are in degrees.. Use oz. copper minimum for top and bottom layer metal.. Vias are required under the backside paddle of this device for proper /DC grounding and thermal dissipation. We recommend a.mm (#/.") diameter bit for drilling via holes and a final plated thru diameter of. mm (. ).. Ensure good package backside paddle solder attach for reliable operation and best electrical performance. Data Sheet July, Subject to change without notice 9 of

10 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Class B ESDA / JEDEC JS-- ESD Charged Device Model (CDM) Class C ESDA / JEDEC JS-- MSL Moisture Sensitivity Level Level IPC/JEDEC J-STD- Caution! ESD-Sensitive Device Solderability Compatible with lead-free ( C max. reflow temp.) soldering process. Solder profiles available upon request. Contact plating: NiPdAu RoHS Compliance This part is compliant with //EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment) as amended by Directive //EU. This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (CHBr) Free PFOS Free SVHC Free Pb Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: Tel: customer.support@qorvo.com For technical questions and application information: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PEORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Data Sheet July, Subject to change without notice of