TQP7M Watt High Linearity Amplifier. General Description. Product Features. Functional Block Diagram. Applications. Ordering Information

Transcription

1 General Description The is a high linearity driver amplifier in industry standard, RoHS compliant, QFN surface mount package. This InGaP / GaAs HBT delivers high performance across 6 27 MHz range of frequencies with 1.8 db Gain, +49. dbm OIP3 and +32. dbm P1dB at 2.14 GHz while only consuming 4 ma quiescent collector current. All devices are 1% RF and DC tested. The incorporates on-chip features that differentiate it from other products in the market. The amplifier integrates an on-chip DC over-voltage and RF over-drive protection. This protects the amplifier from electrical DC voltage surges and high input RF input power levels that may occur in a system. The is targeted for use as a driver amplifier in wireless infrastructure where high linearity, medium power, and high efficiency are required. The device is an excellent candidate for transceiver line cards and high power amplifiers in current and next generation multicarrier 3G / 4G base stations. Functional Block Diagram 24 Pin 4 mm x 4 mm leadless SMT Package Product Features 6 27 MHz dbm P1dB +49. dbm Output IP3 1.8 db Gain At 4 MHz + V Single Supply, 4 ma Collector Current Internal RF Overdrive Protection Internal DC Overvoltage Protection Internal Active Bias On Chip ESD Protection Shut-down Capability Capable Of Handling 1:1 VSWR At + VCC, 2.14 GHz, dbm CW POUT Or +23. dbm WCDMA POUT Applications Vbias Iref /Vcc 1 /Vcc 14 /Vcc Repeaters BTS Transceivers BTS High Power Amplifiers CDMA / WCDMA / LTE General Purpose Wireless Backside Paddle - RF/DC Ground Ordering Information Part No. Description 2 Watt High Linearity Amplifier -PCB MHz EVB -PCB GHz EVB Standard T / R size = 2 pieces on a 13 reel. Data Sheet, June 3, 17 Subject to change without notice 1 of 17

2 Recommended Operating Conditions Parameter Min Typ Max Units Electrical specifications are measured at specified VCC V TCASE 4 +8 C Tj (for>1 6 hours MTTF) 17 C Absolute Maximum Ratings test conditions. Specifications are not guaranteed over all recommended operating conditions. Parameter Range / Value Units Operation of this device exceeding the parameter ranges given may cause permanent damage. Storage Temperature 6 to +1 C C Device Voltage, VCC +6. V dbm Maximum Input Power, CW +3 dbm V Electrical Specifications Test conditions unless otherwise noted: VCC=+ V, ICQ = 4 ma, Temp=, Using a Application circuit. Parameter Conditions Min Typ Max Units Operational Bandwidth 6 27 MHz Test Frequency 4 MHz Power Gain db Input Return Loss 12 db Output Return Loss 9. db Output IP3 Pout=+17 dbm / tone, f=1 MHz dbm WCDMA Channel Power (1) At dbc ACLR dbm Output P1dB dbm Noise Figure 4.4 db Quiescent Collector Current, Icq 4 49 ma VCC + V IREF ma Thermal Resistance (jnc to case) θ jc 1.7 C / W 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, + MHz offset, PAR = 9.7 db at.1% Prob. Data Sheet, June 3, 17 Subject to change without notice 2 of 17

3 Device Characterization Data Gain (db) Input Reflection Coefficients Swp Max 3GHz Output Reflection Coefficients Swp Max 3GHz Gmax Gain (S) S(1,1) Swp Min.GHz S(2,2) Swp Min.GHz S-Parameters Test Conditions: VCC = + V, ICQ = 4 ma, IREF = ma, T=+2 C, unmatched ohm system, calibrated to device leads Freq (GHz) S11 (db) S11 (ang) S (db) S (ang) S12 (db) S12 (ang) S (db) S (ang) Data Sheet, June 3, 17 Subject to change without notice 3 of 17

4 Reference Design: (61 6 MHz) C7 Vcc +V R6 R7 C7 C13 C17 C1 R6 R uf 632 C17 R3 1 pf L4 R3 C14 L3 R1 L1 B1 C1 C14 L R1 33 nh L3 B1 C1 C1 C11 R2 C1 C C9 C8 U1 C2 C3 1 2 Vbias Iref L1 18 nh 8 J2 RF Input C11 R2 1 C1 C9 C 2.2 nh C8 3 4 U C2 12 pf C3 4.7 pf J3 RF Output pf 6.8 pf 1 pf Components shown on the silkscreen but not on the schematic are not used. 2. Ω resistors may be replaced with copper trace in the target application layout. 3. Iref can be used as device power down current by placing R7 at location R8. 4. The recommended component values are dependent upon the frequency of operation.. All components are of 63 size unless stated on the schematic. 6. R1 is critical for device linearity performance. 7. Critical component placement locations: Distance between right edge of C8 and U1 device package is 3 mil Distance between right edge of C and U1 device package is 336 mil Distance between left edge of C2 and U1 device package is 43 mil Distance between center of C9 and U1 device package is 27 mil Typical Performance: (61 6 MHz) Test conditions unless otherwise noted: VCC = + V, ICQ = 4 ma, IREF = ma, T=+2 C Parameter Typical Value Units Frequency MHz Gain.8.1 db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 (+23 dbm / tone, f = 1 MHz) dbm Channel Power (At dbc ACLR with MHz LTE) db Data Sheet, June 3, 17 Subject to change without notice 4 of 17

5 ACPR (dbc) P1dB (dbm) Gain (db) S11 & S (db) OIP3 (dbm) Performance Plots: (61 6 MHz) Test conditions unless otherwise noted: VCC=+ V, Temp= 23 Gain vs. Frequency Return Loss vs. Frequency OIP3 vs. Pout/tone Frequency (MHz) Input Return Loss Output Return Loss Frequency (MHz) MHz 37 6 MHz 6 MHz Pout/Tone (dbm) - 1C MHz LTE signal, PAR=9.dB ACPR vs Pout 36 P1dB vs Frequency MHz 6 MHz 6 MHz Pout (dbm) Frequency (MHz) Data Sheet, June 3, 17 Subject to change without notice of 17

6 Reference Design: ( MHz) C11 R2 C1 L C9 C8 L4 R3 R Vcc +V C14 U1 R7 L3 R1 C13 L1 B1 C17 C1 C1 C2 C7 C3 J2 RF Input C11 R2 1 C1 pf C14 L 6.8 nh C9 2.7 pf R6 R3 L4 C pf Vbias 24 D3 SMT1G 23 U1 C13.1 uf Iref R7 11 R1 33 nh 63 L3 B1 L1 18 nh 8 C2 8.2 pf C7 1 uf 632 C17 1 pf C1 C1 C3 4.7 pf J3 RF Output 1. Components shown on the silkscreen but not on the schematic are not used. 2. Ω resistors may be replaced with copper trace in the target application layout. 3. Iref can be used as device power down current by placing R7 at location R8. 4. The recommended component values are dependent upon the frequency of operation.. All components are of 63 size unless stated on the schematic. 6. R1 is critical for device linearity performance. 7. Critical component placement locations: Distance between center of C8 and U1 device package is 243 mil (11 at 88 MHz) Distance between center of L and U1 device package is 42 mil (. at 88 MHz) Distance between center of C2 and U1 device package is mil (16.1 at 88 MHz) Distance between center of C9 and U1 device package is 27 mil (12.4 at 88 MHz) Typical Performance: ( MHz) Test conditions unless otherwise noted: VCC = + V, ICQ = 4 ma, IREF = ma, T=+2 C Parameter Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 (+23 dbm / tone, f = 1 MHz) dbm WCDMA Channel Power (At dbc ACLR). 23 db Data Sheet, June 3, 17 Subject to change without notice 6 of 17

7 I CC (ma) OIP3 (dbm) ACLR (dbm) Gain (db) S11, S (db) Performance Plots: ( MHz) Test conditions unless otherwise noted: VCC=+ V, Temp= Gain vs. Frequency Temp.= Return Loss vs. Frequency Temp.= - S -1 S MHz Tone Spacing Temp.= OIP3 vs. Pout / Tone ACLR vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 9.7dB at.1% Probability 3.84 MHz BW Temp.=+2 o C GHz.88 GHz.869 GHz GHz.88 GHz.869 GHz Pout / Tone (dbm) Output Power (dbm) 1,1 1, Collector Current vs. Output Power Frequency :.88 GHz CW Signal Temp.=+2 o C Output Power (dbm) Data Sheet, June 3, 17 Subject to change without notice 7 of 17

8 Application Circuit : -PCB9 (9 96 MHz) Vcc +V C11 R2 C1 L C9 C8 L4 R3 R6 C14 U1 R7 L3 R1 C13 L1 B1 C17 C1 C1 C2 C7 C3 J2 RF Input C11 R2 1 C1 pf C14 C9 2.7 pf L 6.8 nh R6 R3 L4 C pf Vbias 24 D3 SMT1G 23 U1 C13.1 uf Iref R7 11 R1 33 nh 63 L3 B1 L1 18 nh 8 C2 8.2 pf C7 1 uf 632 C pf C1 C1 C3 4.7 pf J3 RF Output 1. See PC Board Layout under Application Information section for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. Ω resistors may be replaced with copper trace in the target application layout. 4. Iref can be used as device power down current by placing R7 at location R8.. The recommended component values are dependent upon the frequency of operation. 6. All components are of 63 size unless stated on the schematic. 7. R1 is critical for device linearity performance. 8. Critical component placement locations: Distance between center of C8 and U1 device package is mil (9.2 at 94 MHz) Distance between center of L and U1 device package is 42 mil (.8 at 94 MHz) Distance between center of C2 and U1 device package is 3 mil (14.7 at 94 MHz) Distance between center of C9 and U1 device package is 27 mil (13.3 at 94 MHz) Data Sheet, June 3, 17 Subject to change without notice 8 of 17

9 Bill of Material Reference Des. Value Description Manuf. Part Number n/a n/a Printed Circuit Board Qorvo n/a n/a Printed Circuit Board Qorvo D3 n/a Zener, dual, SOT-23 various C9 2.7 pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J2R7ABSTR B1, L3, L4, R3 Ω Resistor, Chip, 63, %, 1/16W various L 6.8 nh Inductor, 63, % Toko LL168-FSL6N8 C3 4.7 pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J4R7ABSTR C2, C8 8.2 pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J8R2ABSTR C1 pf Capacitor, Chip, 63, %, V, NPO/COG various C1, C11, C14, C1 Capacitor, Chip, 63, %, V, NPO/COG various L1 18 nh Inductor, 18, %, Coilcraft CS Series Coilcraft 18HQ-18NXJL C17 1 pf Capacitor, Chip, 63, 1%, V, NPO/COG various C13.1 μf Capacitor, Chip, 63, V, XR, 1% various C7 1 μf Capacitor, Tantalum, 632, V, 1% various R2 1 Ω Resistor, Chip, 63, %, 1/16W various R6 2 Ω Resistor, Chip, 63, 1%, 1/16W various R7 11 Ω Resistor, Chip, 63, 1%, 1/16W various R1 33 nh Inductor, 63, % Toko LL168-FSL33N R8, R4, C12, C4,D3 n/a Do Not Place Typical Performance: -PCB9 (9 96 MHz) Test conditions unless otherwise noted: VCC = + V, ICQ = 4 ma, IREF = ma, T=+2 C Parameter Typical Value Units Frequency MHz Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 (+23 dbm/tone, f = 1 MHz) dbm WCDMA Channel power (at dbc ACLR) (1) dbm 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, + MHz offset, PAR = 9.7 db at.1% Prob. Data Sheet, June 3, 17 Subject to change without notice 9 of 17

10 ACLR (dbm) ACLR (dbm) I CC (ma) P1dB (dbm) OIP3 (dbm) OIP3 (dbm) Gain (db) S11 (db) S (db) RF Performance Plots: -PCB9 (9 96 MHz) Test conditions unless otherwise noted: VCC=+ V, Temp= Gain vs. Frequency Input Return Loss vs. Frequency 23 Output Return Loss vs. Frequency C +8 C C +8 C - 4 C +8 C P1dB vs. Temperature +8 C 4 C 1MHz Tone Spacing OIP3 vs. Pout / Tone 1MHz Tone Spacing Temp.=+2 o C OIP3 vs. Output Power C +8 C GHz.94 GHz.92 GHz Pout / Tone(dBm) Output Power / Tone (dbm) -4-4 ACLR vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 9.7dB at.1% Probability 3.84 MHz BW Frequency :.94 GHz -4-4 ACLR vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH Temp.=+2 o C PAR = 9.7dB at.1% Probability 3.84 MHz BW 1,1 1, 9 Collector Current vs. Output Power Frequency :.94 GHz CW Signal Temp.=+2 o C C +8 C GHz.94 GHz.92 GHz Output Power (dbm) Output Power (dbm) Output Power (dbm) Data Sheet, June 3, 17 Subject to change without notice 1 of 17

11 7 8 9 Application Circuit: -PCB4 (1 7 MHz) Vcc +V C11 R2 C1 C9 L4 R3 R6 C8 C14 U1 R7 C13 L3 R1 C2 L1 B1 C17 C1 C1 C7 C3 J2 RF Input C11 C14 R2 1 C1 pf R6 R3 L C pf C pf Vbias 24 D3 SMT1G 23 U1 C13.1 uf Iref R7 11 R1 1 nh 63 L3 B1 L1 18 nh 8 C2 2.7 pf C7 1 uf 632 C17 1 pf C1 C1 pf C3 J3 RF Output 1. See PC Board Layout under Application Information section for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. Ω resistors may be replaced with copper trace in the target application layout. 4. Iref can be used as device power down current by placing R7 at location R8.. The recommended component values are dependent upon the frequency of operation. 6. All components are of 63 size unless stated on the schematic. 7. R1 is critical for device linearity performance. 8. Critical component placement locations: Distance between center of C8 and U1 device package is mil (. at 4 MHz) Distance between center of C2 and U1 device package is 113 mil (12.4 at 4 MHz) Distance between center of C9 and U1 device package is 27 mil (3.3 at 4 MHz) Data Sheet, June 3, 17 Subject to change without notice 11 of 17

12 Bill of Material -PCB4 Reference Des. Value Description Manuf. Part Number U1 n/a 2W High Linearity Amplifier Qorvo n/a n/a Printed Circuit Board Qorvo D3 n/a Zener, dual, SOT-23 various C8 1. pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J1RABSTR C9 2.4 pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J2R4ABSTR C2 2.7 pf Capacitor, Chip, 63, ±.pf, V, Accu-P AVX 6J2R7ABSTR B1, L3, L4, R3, C11 Ω Resistor, Chip, 63, %, 1/16W various C1, C1 pf Capacitor, Chip, 63, %, V, NPO/COG various C1, C14, C3 Capacitor, Chip, 63, %, V, NPO/COG various L1 18 nh Inductor, 18, %, Ceramic Coilcraft 18HQ-18NXJL C17 1 pf Capacitor, Chip, 63, 1%, V, NPO/COG various C13.1 μf Capacitor, Chip, 63, 1%, V, XR various C7 1 μf Capacitor, Tantalum, 632, %, V various R2 1 Ω Resistor, Chip, 63, %, 1/16W various R6 2 Ω Resistor, Chip, 63, 1%, 1/16W various R7 11 Ω Resistor, Chip, 63, 1%, 1/16W various R1 1 nh Inductor, 63, % Toko LL168-FSR12J R8, R4, C12, C4, D3 n/a Do Not Place Data Sheet, June 3, 17 Subject to change without notice 12 of 17

13 S (db) P1dB (dbm) Gain (db) S11 (db) Typical Performance: -PCB4 (1 7 MHz) Test conditions unless otherwise noted: VCC = + V, ICQ = 4 ma, IREF = ma Parameter Typical Value Units Frequency MHz Gain db Input Return Loss db Output Return Loss db Output P1dB dbm Output IP3 (+17 dbm / tone, f = 1 MHz) dbm WCDMA Channel power (at dbc ACLR) (1) dbm Noise Figure db 1. ACLR Test set-up: 3GPP WCDMA, TM1+64 DPCH, + MHz offset, PAR = 9.7 db at.1% Prob. RF Performance Plots: -PCB4 (1 7 MHz) Test conditions unless otherwise noted: VCC=+ V, Temp=+2 C 18 Gain vs. Frequency Input Return Loss vs. Frequency C +8 C C +8 C Output Return Loss vs. Frequency - 4 C +8 C P1dB vs. Temperature +8 C 4 C Data Sheet, June 3, 17 Subject to change without notice 13 of 17

14 Collector Current (ma) NF (db) ACLR (dbm) ACLR (dbm) OIP3 (dbm) OIP3 (dbm) RF Performance Plots: -PCB4 (1 7 MHz) 1MHz Tone Spacing OIP3 vs. Pout / Tone OIP3 vs. Output Power vs. Frequency 1MHz Tone Spacing Temp.=+2 o C C +8 C GHz 2.14 GHz 2.11 GHz Pout / Tone(dBm) -4-4 ACLR vs. Pout / Tone W-CDMA 3GPP Test Model 1+64 DPCH PAR = 9.7dB at.1% Probability 3.84 MHz BW Frequency : 2.14 GHz Output Power / Tone(dBm) -4-4 ACLR vs. Output Power W-CDMA 3GPP Test Model 1+64 DPCH PAR = 9.7dB at.1% Probability 3.84 MHz BW Temp.=+2 o C C 4 C GHz 2.14 GHz 2.11 GHz Pout / Tone (dbm) 1, 9 8 Frequency : 2.14 GHz CW Signal Temp.=+2 o C I CC vs. Output Power Output Power (dbm) 6.. Noise Figure vs. Frequency Temp.= Output Power (dbm) Data Sheet, June 3, 17 Subject to change without notice 14 of 17

15 Pin Configuration and Description Vbias Iref /Vcc 1 /Vcc 14 /Vcc Backside Paddle - RF/DC Ground Pin No. Symbol Description 1 VBIAS Voltage supply for active bias for the amp. Connect to same supply voltage as Vcc. 2, 3, 6,7, 8, 9, 1, 11, 12, 13,17,,,, GND / NC No internal connection. This pin can be grounded or N/C on PCB. Land pads should be provided for PCB mounting integrity., 23, 24 4, RFIN RF Input. DC voltage present, blocking capacitor required. Requires external match for optimal performance. 14, 1, 16 RFOUT / VCC RF Output. DC Voltage present, blocking cap required. Requires external match for optimal performance. 18 IREF Reference current into internal active bias current mirror. Current into Iref sets device quiescent current. Also, can be used as on/off control. Backside paddle RF / DC GND Multiple Vias should be employed to minimize inductance and thermal resistance. Use recommended via pattern shown under mounting configuration and ensure good solder attach for optimum thermal and electrical performance Data Sheet, June 3, 17 Subject to change without notice 1 of 17

16 Package Marking and Dimensions Marking: Part Identifier 7M914 Date Code YYMM Lot code AaXXXX TERMINAL #1 IDENTIFIER X. Pitch 24X.2±. Pin #1 IDENTIFIER CHAMFER.3 x 4 24X.4±. 4 7M914 YYMM AaXXXX ±. 6 Exp. DAP R.7 2. Ref. 24X.1 C.8 C...3 Ref..8±. C SEATING PLANE 2.7±. Exp. DAP GND/THERMAL PAD 1. All dimensions are in millimeters. Angles are in degrees. 2. Except where noted, this part outline conforms to JEDEC standard MO-2, Issue E (Variation VGGC) for thermally enhanced plastic very thin fine pitch quad flat no lead package (QFN). 3. Dimension and tolerance formats conform to ASME Y14.4M The terminal #1 identifier and terminal numbering conform to JESD 9-1 SPP-12.. Co-planarity applies to the exposed ground/thermal pad as well as the contact pins. 6. Package body length/width does not include plastic flash protrusion across mold parting line. PCB Mounting Pattern 3 16X PACKAGE OUTLINE X X.38. PITCH R (SOLDER MASK) MINIMUM BACKSIDE THERMAL CONTACT AREA COMPONENT SIDE BACK SIDE 1. All dimensions are in millimeters. Angles are in degrees. 2. Use 1 oz. copper minimum for top and bottom layer metal. 3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We recommend a.mm (#8/.1") diameter bit for drilling via holes and a final plated thru diameter of.2mm (.1 ). 4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.. Place mounting screws near the part to fasten a back side heat sink. 6. Do not apply solder mask to the back side of the PC board in the heat sink contact region. 7. Ensure that the backside via region makes good physical contact with the heat sink. Data Sheet, June 3, 17 Subject to change without notice 16 of 17

17 Handling Precautions Parameter Rating Standard ESD Human Body Model (HBM) Class 1C ESDA / JEDEC JS-1-12 ESD Charged Device Model (CDM) Class C3 JEDEC JESD-C11F MSL Moisture Sensitivity Level Level 1 IPC/JEDEC J-STD- Caution! ESD-Sensitive Device Solderability Compatible with both lead-free (26 C max. reflow temp.) and tin/lead (24 C max. reflow temp.) soldering processes. Solder profiles available upon request. Contact plating: Annealed Matte Tin over Copper RoHS Compliance This part is compliant with the 11/6/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment) as amended by Directive 1/863/EU. This product also has the following attributes: Product uses RoHS Exemption 7c-I to meet RoHS Compliance requirements. Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C1H12Br42) Free PFOS Free SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: Tel: customer.support@qorvo.com For technical questions and application information: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 16 Qorvo, Inc. Qorvo is a registered trademark of Qorvo, Inc. Data Sheet, June 3, 17 Subject to change without notice 17 of 17